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Eliminate SET_NB_CFG_54 option. There was no board that 

deselected it, and very likely there won't ever be any
hardware that requires it deselected.

Keep the "selected" code path around, leading to no
functional change.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Scott Duplichan <scott@notabs.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-11-18 00:11:32 +00:00 committed by Patrick Georgi
parent 361bd10bce
commit d28c2986d6
64 changed files with 0 additions and 236 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/cpu/amd/dualcore/dualcore.c
View File

@ -1,10 +1,5 @@
/* 2004.12 yhlu add dual core support */
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore_id.c"
#include <pc80/mc146818rtc.h>
#if CONFIG_HAVE_OPTION_TABLE
@ -20,7 +15,6 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
return dword;
}
#if SET_NB_CFG_54 == 1
static inline uint8_t set_apicid_cpuid_lo(void)
{
#if CONFIG_K8_REV_F_SUPPORT == 0
@ -35,11 +29,6 @@ static inline uint8_t set_apicid_cpuid_lo(void)
return 1;
}
#else
static inline void set_apicid_cpuid_lo(void) { }
#endif
static inline void real_start_other_core(unsigned nodeid)
{

11
src/cpu/amd/quadcore/quadcore.c
View File

@ -24,10 +24,6 @@
#include "option_table.h"
#endif
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/quadcore/quadcore_id.c"
static u32 get_core_num_in_bsp(u32 nodeid)
@ -43,7 +39,6 @@ static u32 get_core_num_in_bsp(u32 nodeid)
return dword;
}
#if SET_NB_CFG_54 == 1
static u8 set_apicid_cpuid_lo(void)
{
// set the NB_CFG[54]=1; why the OS will be happy with that ???
@ -54,12 +49,6 @@ static u8 set_apicid_cpuid_lo(void)
return 1;
}
#else
static void set_apicid_cpuid_lo(void) { }
#endif
static void real_start_other_core(u32 nodeid, u32 cores)
{

4
src/mainboard/amd/dbm690t/romstage.c
View File

@ -17,10 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define RC0 (6<<8)
#define RC1 (7<<8)

4
src/mainboard/amd/mahogany/romstage.c
View File

@ -17,10 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define RC0 (6<<8)
#define RC1 (7<<8)

2
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -21,8 +21,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

4
src/mainboard/amd/pistachio/romstage.c
View File

@ -17,10 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define DIMM0 0x50
#define DIMM1 0x51

2
src/mainboard/amd/serengeti_cheetah/ap_romstage.c
View File

@ -1,8 +1,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define SET_NB_CFG_54 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

2
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -1,5 +1,3 @@
#define SET_NB_CFG_54 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -21,8 +21,6 @@
//#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

2
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -21,8 +21,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

3
src/mainboard/arima/hdama/romstage.c
View File

@ -73,9 +73,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"

4
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -18,10 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define RC0 (6<<8)
#define RC1 (7<<8)

4
src/mainboard/asus/a8n_e/romstage.c
View File

@ -24,10 +24,6 @@
/* Used by it8712f_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

2
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -21,8 +21,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

5
src/mainboard/broadcom/blast/romstage.c
View File

@ -1,8 +1,3 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

2
src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
View File

@ -24,8 +24,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define SET_NB_CFG_54 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -21,10 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/gigabyte/m57sli/ap_romstage.c
View File

@ -22,8 +22,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define SET_NB_CFG_54 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -19,10 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -21,8 +21,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

2
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -21,8 +21,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

5
src/mainboard/hp/dl145_g1/romstage.c
View File

@ -1,8 +1,3 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

4
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -25,10 +25,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

5
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -28,11 +28,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

4
src/mainboard/ibm/e325/romstage.c
View File

@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -70,9 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"

4
src/mainboard/ibm/e326/romstage.c
View File

@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -70,9 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"

4
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -21,10 +21,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
//used by raminit
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

2
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -1,5 +1,3 @@
#define SET_NB_CFG_54 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -1,5 +1,3 @@
#define SET_NB_CFG_54 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/iwill/dk8x/romstage.c
View File

@ -1,5 +1,3 @@
#define SET_NB_CFG_54 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -22,8 +22,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define SET_NB_CFG_54 1
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

4
src/mainboard/kontron/kt690/romstage.c
View File

@ -18,10 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define RC0 (6<<8)
#define RC1 (7<<8)

4
src/mainboard/msi/ms7135/romstage.c
View File

@ -24,10 +24,6 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

1
src/mainboard/msi/ms7260/ap_romstage.c
View File

@ -23,7 +23,6 @@
#define __PRE_RAM__
#define SET_NB_CFG_54 1 /* Used by RAM init. */
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/msi/ms7260/romstage.c
View File

@ -20,10 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/msi/ms9185/romstage.c
View File

@ -23,8 +23,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define SET_NB_CFG_54 1
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

2
src/mainboard/msi/ms9282/romstage.c
View File

@ -22,8 +22,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define SET_NB_CFG_54 1
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

5
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -22,11 +22,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

4
src/mainboard/newisys/khepri/romstage.c
View File

@ -4,7 +4,6 @@
* Additional (C) 2007 coresystems GmbH
*/
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -80,9 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* newisys khepri does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"

2
src/mainboard/nvidia/l1_2pvv/ap_romstage.c
View File

@ -22,8 +22,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define SET_NB_CFG_54 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -19,10 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

5
src/mainboard/sunw/ultra40/romstage.c
View File

@ -1,8 +1,3 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

2
src/mainboard/supermicro/h8dme/ap_romstage.c
View File

@ -22,8 +22,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define SET_NB_CFG_54 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -16,10 +16,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

2
src/mainboard/supermicro/h8dmr/ap_romstage.c
View File

@ -22,8 +22,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define SET_NB_CFG_54 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -19,10 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

5
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -22,11 +22,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

5
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -22,11 +22,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

4
src/mainboard/technexion/tim5690/romstage.c
View File

@ -17,10 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define RC0 (6<<8)
#define RC1 (7<<8)

4
src/mainboard/technexion/tim8690/romstage.c
View File

@ -17,10 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define RC0 (6<<8)
#define RC1 (7<<8)

4
src/mainboard/tyan/s2850/romstage.c
View File

@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -67,9 +66,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"

4
src/mainboard/tyan/s2875/romstage.c
View File

@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -68,9 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"

4
src/mainboard/tyan/s2880/romstage.c
View File

@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -68,9 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"

5
src/mainboard/tyan/s2881/romstage.c
View File

@ -1,8 +1,3 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

4
src/mainboard/tyan/s2882/romstage.c
View File

@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -68,9 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"

4
src/mainboard/tyan/s2885/romstage.c
View File

@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -70,9 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"

4
src/mainboard/tyan/s2891/romstage.c
View File

@ -1,7 +1,3 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

5
src/mainboard/tyan/s2892/romstage.c
View File

@ -1,8 +1,3 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

4
src/mainboard/tyan/s2895/romstage.c
View File

@ -1,7 +1,3 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

2
src/mainboard/tyan/s2912/ap_romstage.c
View File

@ -22,8 +22,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define SET_NB_CFG_54 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/tyan/s2912/romstage.c
View File

@ -19,10 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif

5
src/mainboard/tyan/s2912_fam10/romstage.c
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@ -22,11 +22,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>

4
src/mainboard/tyan/s4880/romstage.c
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@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -84,9 +83,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"
#define RC0 ((1<<2)<<8)

4
src/mainboard/tyan/s4882/romstage.c
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@ -1,4 +1,3 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -92,9 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c"
#define RC0 ((1<<2)<<8)