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sb/intel/bd82x6x/lpc: Set up default LPC decode ranges 

This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2019-06-16 23:36:28 +02:00 committed by Patrick Georgi
parent a06689c7e7
commit d28d507190
37 changed files with 18 additions and 193 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/asrock/b75pro3-m/romstage.c
View File

@ -25,9 +25,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000);
}
void mainboard_rcba_config(void)

1
src/mainboard/asus/h61m-cs/romstage.c
View File

@ -29,7 +29,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

1
src/mainboard/asus/maximus_iv_gene-z/romstage.c
View File

@ -42,7 +42,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
void pch_enable_lpc(void)
{
pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

6
src/mainboard/asus/p8z77-m_pro/romstage.c
View File

@ -32,12 +32,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF1_LPC_EN | CNF2_LPC_EN |
KBC_LPC_EN | COMB_LPC_EN);
/* Set COMB/COM2 IO range to 2F8h-2FFh */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
}
void mainboard_rcba_config(void)

3
src/mainboard/compulab/intense_pc/romstage.c
View File

@ -26,9 +26,6 @@ void pch_enable_lpc(void)
{
pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
/* Enable SuperIO */
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);

5
src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
View File

@ -27,11 +27,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

6
src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
View File

@ -25,12 +25,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN);
if (!CONFIG(NO_UART_ON_SUPERIO)) {
pci_or_config16(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
}
}
void mainboard_rcba_config(void)

3
src/mainboard/google/link/romstage.c
View File

@ -34,9 +34,6 @@
void pch_enable_lpc(void)
{
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
GAMEL_LPC_EN | COMA_LPC_EN);

3
src/mainboard/google/parrot/romstage.c
View File

@ -28,9 +28,6 @@
void pch_enable_lpc(void)
{
/* Parrot EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
}
void mainboard_rcba_config(void)

6
src/mainboard/hp/2570p/romstage.c
View File

@ -22,12 +22,6 @@
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

6
src/mainboard/hp/2760p/romstage.c
View File

@ -21,12 +21,6 @@
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

9
src/mainboard/hp/8460p/romstage.c
View File

@ -25,15 +25,6 @@
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
* Enable parallel port and serial port
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
}
void mainboard_rcba_config(void)

9
src/mainboard/hp/8470p/romstage.c
View File

@ -24,15 +24,6 @@
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
* Enable parallel port and serial port
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
}
void mainboard_rcba_config(void)

9
src/mainboard/hp/8770w/romstage.c
View File

@ -25,15 +25,6 @@
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
* Enable parallel port and serial port
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
}
void mainboard_rcba_config(void)

10
src/mainboard/hp/compaq_8200_elite_sff/romstage.c
View File

@ -29,16 +29,6 @@
void pch_enable_lpc(void)
{
/*
* Enable SuperIO, TPM, Keyboard, LPT, COMA
* (COMB can be equip on expansion header)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN |CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN |
COMB_LPC_EN | COMA_LPC_EN);
/* COMA: 3F8h, COMB: 2F8h */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
}
void mainboard_rcba_config(void)

7
src/mainboard/hp/folio_9470m/romstage.c
View File

@ -23,13 +23,6 @@
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
}
void mainboard_rcba_config(void)

7
src/mainboard/hp/revolve_810_g1/romstage.c
View File

@ -26,13 +26,6 @@
void pch_enable_lpc(void)
{
/*
* CNF2 and CNF1 for Super I/O
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
}
void mainboard_rcba_config(void)

10
src/mainboard/hp/z220_sff_workstation/romstage.c
View File

@ -29,16 +29,6 @@
void pch_enable_lpc(void)
{
/*
* Enable SuperIO, TPM, Keyboard, LPT, COMA
* (COMB can be equip on expansion header)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN |
COMB_LPC_EN | COMA_LPC_EN);
/* COMA: 3F8h, COMB: 2F8h */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
}
void mainboard_rcba_config(void)

10
src/mainboard/intel/dcp847ske/early_southbridge.c
View File

@ -27,18 +27,8 @@
#include "superio.h"
#include "thermal.h"
#if CONFIG(DISABLE_UART_ON_TESTPADS)
#define DEBUG_UART_EN 0
#else
#define DEBUG_UART_EN COMA_LPC_EN
#endif
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
CNF2_LPC_EN | DEBUG_UART_EN);
/* Decode SuperIO 0x0a00 */
pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
}
void mainboard_rcba_config(void)

3
src/mainboard/intel/emeraldlake2/romstage.c
View File

@ -32,9 +32,6 @@ void pch_enable_lpc(void)
{
pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
/* Enable SuperIO + PS/2 Keyboard/Mouse */
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);

5
src/mainboard/lenovo/l520/romstage.c
View File

@ -24,11 +24,6 @@
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse, LPT */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN);
}
void mainboard_rcba_config(void)

1
src/mainboard/lenovo/s230u/romstage.c
View File

@ -29,7 +29,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */

5
src/mainboard/lenovo/t420/romstage.c
View File

@ -51,11 +51,6 @@ static void hybrid_graphics_init(void)
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

5
src/mainboard/lenovo/t420s/romstage.c
View File

@ -51,11 +51,6 @@ static void hybrid_graphics_init(void)
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

4
src/mainboard/lenovo/t430/romstage.c
View File

@ -51,10 +51,6 @@ static void hybrid_graphics_init(void)
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

5
src/mainboard/lenovo/t430s/romstage.c
View File

@ -21,11 +21,6 @@
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

5
src/mainboard/lenovo/t520/romstage.c
View File

@ -53,11 +53,6 @@ static void hybrid_graphics_init(void)
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

5
src/mainboard/lenovo/t530/romstage.c
View File

@ -53,11 +53,6 @@ static void hybrid_graphics_init(void)
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

4
src/mainboard/lenovo/x131e/romstage.c
View File

@ -22,10 +22,6 @@
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

5
src/mainboard/lenovo/x1_carbon_gen1/romstage.c
View File

@ -30,11 +30,6 @@
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

5
src/mainboard/lenovo/x220/romstage.c
View File

@ -29,11 +29,6 @@
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

5
src/mainboard/lenovo/x230/romstage.c
View File

@ -26,11 +26,6 @@
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

5
src/mainboard/msi/ms7707/romstage.c
View File

@ -23,11 +23,6 @@
void pch_enable_lpc(void)
{
/* IO Decode Ranges Register */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
/* LPC IF Enables Register (CNF2_LPC_EN|KBC_LPC_EN) */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
u16 reg16;
reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);
reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD)

4
src/mainboard/roda/rv11/variants/rv11/romstage.c
View File

@ -23,10 +23,6 @@
void pch_enable_lpc(void)
{
/* Enable KBC on 0x60/0x64 (KBC),
EC on 0x62/0x66 (MC) */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
KBC_LPC_EN | MC_LPC_EN);
}
void mainboard_config_superio(void)

8
src/mainboard/roda/rv11/variants/rw11/romstage.c
View File

@ -27,14 +27,6 @@
void pch_enable_lpc(void)
{
/* COMA on 0x3f8, COMB on 0x2f8 */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable KBC on 0x60/0x64 (KBC),
EC on 0x62/0x66 (MC),
SIO on 0x2e/0x2f (CNF1) */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
COMB_LPC_EN | COMA_LPC_EN);
}
void mainboard_config_superio(void)

2
src/mainboard/sapphire/pureplatinumh61/romstage.c
View File

@ -23,8 +23,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
}

21
src/southbridge/intel/bd82x6x/early_pch.c
View File

@ -254,8 +254,22 @@ static void pch_generic_setup(void)
write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */
}
static void pch_enable_lpc_gen_decode(void)
static void pch_enable_lpc_decode(void)
{
/*
* Enable some common LPC IO ranges:
* - 0x2e/0x2f, 0x4e/0x4f often SuperIO
* - 0x60/0x64, 0x62/0x66 often KBC/EC
* - 0x3f0-0x3f5/0x3f7 FDD
* - 0x378-0x37f and 0x778-0x77f LPT
* - 0x2f8-0x2ff COMB
* - 0x3f8-0x3ff COMA
*/
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
| MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
const struct device *dev = pcidev_on_root(0x1f, 0);
const struct southbridge_intel_bd82x6x_config *config = NULL;
@ -275,9 +289,10 @@ static void pch_enable_lpc_gen_decode(void)
void early_pch_init(void)
{
pch_enable_lpc();
pch_enable_lpc_gen_decode();
pch_enable_lpc_decode();
pch_enable_lpc();
pch_enable_bars();