GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

stumpy: Add native raminit support 

Change-Id: Ibbb056ae209a16533757af925c8c833c94803834
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13662
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Vladimir Serbinenko 2016-02-10 02:52:42 +01:00
parent b2ad8108ab
commit d2990c90fd
3 changed files with 32 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/samsung/stumpy/Kconfig
View File

@ -15,12 +15,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# LPC47N207 selected for external LPC card # LPC47N207 selected for external LPC card
# not on board, should be made selectable. # not on board, should be made selectable.
select SUPERIO_SMSC_LPC47N207 select SUPERIO_SMSC_LPC47N207
select HAVE_MRC
select INTEL_INT15 select INTEL_INT15
config USE_NATIVE_RAMINIT if !USE_NATIVE_RAMINIT
bool config BOARD_SPECIFIC_OPTIONS_MRC # dummy
default n def_bool y
select HAVE_MRC
endif
config CHROMEOS config CHROMEOS
select PHYSICAL_REC_SWITCH select PHYSICAL_REC_SWITCH

2
src/mainboard/samsung/stumpy/devicetree.cb
View File

@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge
# Enable DVI Hotplug with 6ms pulse # Enable DVI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06" register "gpu_dp_b_hotplug" = "0x06"
register "max_mem_clock_mhz" = "666"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989 chip cpu/intel/socket_rPGA989
device lapic 0 on end device lapic 0 on end

25
src/mainboard/samsung/stumpy/romstage.c
View File

@ -31,6 +31,7 @@
#include <superio/ite/it8772f/it8772f.h> #include <superio/ite/it8772f/it8772f.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
@ -203,6 +204,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
*pei_data = pei_data_template; *pei_data = pei_data_template;
} }
void mainboard_get_spd(spd_raw_data *spd)
{
read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x52);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled power usb oc pin */
{ 1, 1, 0 }, /* P0: Front port (OC0) */
{ 1, 0, 1 }, /* P1: Back port (OC1) */
{ 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, -1 }, /* P3: MMC (no OC) */
{ 1, 1, 2 }, /* P4: Front port (OC2) */
{ 0, 0, -1 }, /* P5: Empty */
{ 0, 0, -1 }, /* P6: Empty */
{ 0, 0, -1 }, /* P7: Empty */
{ 1, 0, 4 }, /* P8: Back port (OC4) */
{ 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
{ 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
{ 0, 0, -1 }, /* P11: Empty */
{ 1, 0, 6 }, /* P12: Back port (OC6) */
{ 1, 0, 5 }, /* P13: Back port (OC5) */
};
void mainboard_early_init(int s3resume) void mainboard_early_init(int s3resume)
{ {
init_bootmode_straps(); init_bootmode_straps();