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mb/asrock: Drop unneeded empty lines 

Change-Id: I4385fded02e43f3fd8683dd926d81a59c04d3bd9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2020-08-19 21:53:19 +02:00 committed by Patrick Georgi
parent 3cb8abd1b6
commit d2a00d7a1c
7 changed files with 0 additions and 9 deletions
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1
src/mainboard/asrock/e350m1/BiosCallOuts.c
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@ -6,7 +6,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h> #include <SB800.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] = const BIOS_CALLOUT_STRUCT BiosCallouts[] =

2
src/mainboard/asrock/e350m1/mptable.c
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h> #include <arch/io.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
@ -9,7 +8,6 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
u8 intr_data[] = { u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */

2
src/mainboard/asrock/e350m1/platform_cfg.h
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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _PLATFORM_CFG_H_ #ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_
@ -109,7 +108,6 @@
*/ */
#define SATA_PORT_MULT_CAP_RESERVED 1 #define SATA_PORT_MULT_CAP_RESERVED 1
/** /**
* @def AZALIA_AUTO * @def AZALIA_AUTO
* @brief Detect Azalia controller automatically. * @brief Detect Azalia controller automatically.

1
src/mainboard/asrock/g41c-gs/hda_verb.c
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@ -32,7 +32,6 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(1, 0x03, 0x18560010), AZALIA_PIN_CFG(1, 0x03, 0x18560010),
/* coreboot specific header */ /* coreboot specific header */
/* Realtek ALC662 rev1 */ /* Realtek ALC662 rev1 */
0x10ec0662, /* Vendor ID */ 0x10ec0662, /* Vendor ID */

1
src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c
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@ -88,7 +88,6 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio33 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH,
}; };
const struct pch_gpio_map mainboard_gpio_map = { const struct pch_gpio_map mainboard_gpio_map = {
.set1 = { .set1 = {
.mode = &pch_gpio_set1_mode, .mode = &pch_gpio_set1_mode,

1
src/mainboard/asrock/imb-a180/OemCustomize.c
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@ -5,7 +5,6 @@
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,

1
src/mainboard/asrock/imb-a180/mptable.c
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@ -7,7 +7,6 @@
#include <stdint.h> #include <stdint.h>
#include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/hudson.h>
u8 picr_data[0x54] = { u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,