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mb/intel/ehlcrb: Add initial mainboard code 

This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.

This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868

List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
   config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs
 2. Clean up devicetree as per tigerlake SOC
 3. Add GPIO support
 4. Update ehl fmd file to replace 32MB chromeos.fmd

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Tan, Lean Sheng 2020-11-18 04:37:59 -08:00 committed by Patrick Georgi
parent b89ce115da
commit d2afd87b0d
23 changed files with 917 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
src/mainboard/intel/elkhartlake_crb/Kconfig Normal file
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if BOARD_INTEL_ELKHARTLAKE_CRB
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DPTF_USE_EISA_HID
select DRIVERS_I2C_DA7219
select DRIVERS_I2C_HID
select DRIVERS_INTEL_DPTF
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_MAX98373
select DRIVERS_INTEL_MIPI_CAMERA
select DRIVERS_SPI_ACPI
select DRIVERS_USB_ACPI
select EC_ACPI
select HAVE_SPD_IN_CBFS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_ELKHARTLAKE
select SOC_INTEL_COMMON_BLOCK_DTT
select SOC_INTEL_CSE_LITE_SKU
config MAINBOARD_DIR
string
default "intel/elkhartlake_crb"
config VARIANT_DIR
string
default "ehlcrb" if BOARD_INTEL_ELKHARTLAKE_CRB
config MAINBOARD_PART_NUMBER
string
default "ehlcrb"
config MAINBOARD_FAMILY
string
default "Intel_ehlcrb"
config DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
config DIMM_SPD_SIZE
int
default 512
config CHROMEOS
bool
default y
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
select GBB_FLAG_FORCE_MANUAL_RECOVERY
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2
config UART_FOR_CONSOLE
int
default 2 if INTEL_LPSS_UART_FOR_CONSOLE
default 0
config TPM_TIS_ACPI_INTERRUPT
int
default 45 # GPE0_DW1_13 (GPP_H13)
endif

2
src/mainboard/intel/elkhartlake_crb/Kconfig.name Normal file
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config BOARD_INTEL_ELKHARTLAKE_CRB
bool "Elkhartlake LPDDR4x CRB"

24
src/mainboard/intel/elkhartlake_crb/Makefile.inc Normal file
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## SPDX-License-Identifier: GPL-2.0-only
subdirs-y += spd
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += romstage_fsp_params.c
romstage-y += board_id.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
ramstage-y += board_id.c
smm-y += smihandler.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
subdirs-y += variants/$(VARIANT_DIR)

43
src/mainboard/intel/elkhartlake_crb/board_id.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <boardid.h>
#include <ec/acpi/ec.h>
#include <ec/google/chromeec/ec.h>
#include <stdint.h>
#include "board_id.h"
static uint32_t get_board_id_via_ext_ec(void)
{
uint32_t id = BOARD_ID_INIT;
if (google_chromeec_get_board_version(&id))
id = BOARD_ID_UNKNOWN;
return id;
}
/*
* Get Board ID via EC I/O port write/read
* Board id is 5 bit, so mask other bits while returning board id.
*/
int get_board_id(void)
{
MAYBE_STATIC_NONZERO int id = -1;
if (id < 0) {
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
id = get_board_id_via_ext_ec();
} else {
uint8_t buffer[2];
uint8_t index;
if (send_ec_command(EC_FAB_ID_CMD) == 0) {
for (index = 0; index < sizeof(buffer); index++)
buffer[index] = recv_ec_data();
id = (buffer[0] << 8) | buffer[1];
}
}
}
return (id & 0x1f);
}

15
src/mainboard/intel/elkhartlake_crb/board_id.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
#define _MAINBOARD_COMMON_BOARD_ID_H_
/* Board/FAB ID Command */
#define EC_FAB_ID_CMD 0x0D
/*
* Returns board information (board id[15:8] and
* Fab info[7:0]) on success and < 0 on error
*/
int get_board_id(void);
#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */

5
src/mainboard/intel/elkhartlake_crb/board_info.txt Normal file
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Vendor name: Intel
Board name: Elkhartlake CRB
Category: eval
ROM protocol: SPI
ROM socketed: n

15
src/mainboard/intel/elkhartlake_crb/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <bootblock_common.h>
#include <soc/gpio.h>
void bootblock_mainboard_init(void)
{
const struct pad_config *pads;
size_t num;
pads = variant_early_gpio_table(&num);
gpio_configure_pads(pads, num);
}

46
src/mainboard/intel/elkhartlake_crb/chromeos.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
int get_lid_switch(void)
{
/* Lid always open */
return 1;
}
int get_recovery_mode_switch(void)
{
return 0;
}
#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
int get_write_protect_state(void)
{
/* No write protect */
return 0;
}
void mainboard_chromeos_acpi_generate(void)
{
const struct cros_gpio *gpios;
size_t num;
gpios = variant_cros_gpios(&num);
chromeos_acpi_gpio_generate(gpios, num);
}

43
src/mainboard/intel/elkhartlake_crb/chromeos.fmd Normal file
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FLASH@0xff000000 0x1000000 {
SI_ALL@0x0 0x600000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x80000
SI_ME@0x81000 0x57F000
}
SI_BIOS@0x600000 0xA00000 {
RW_SECTION_A@0x0 0x2d0000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x2bffc0
RW_FWID_A@0x2cffc0 0x40
}
RW_SECTION_B@0x2d0000 0x2d0000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x2bffc0
RW_FWID_B@0x2cffc0 0x40
}
RW_MISC@0x5a0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG(PRESERVE)@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD(PRESERVE)@0x28000 0x2000
RW_NVRAM(PRESERVE)@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x5d0000 0x30000
WP_RO@0x600000 0x400000 {
RO_VPD(PRESERVE)@0x0 0x4000
RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0x3000
COREBOOT(CBFS)@0x4000 0x3f8000
}
}
}
}

49
src/mainboard/intel/elkhartlake_crb/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <baseboard/ec.h>
#include <baseboard/gpio.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 /* OEM revision */
)
{
#include <soc/intel/common/block/acpi/acpi/platform.asl>
/* global NVS and variables */
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/elkhartlake/acpi/southbridge.asl>
}
}
#if CONFIG(CHROMEOS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
#endif
#include <southbridge/intel/common/acpi/sleepstates.asl>
}

40
src/mainboard/intel/elkhartlake_crb/mainboard.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <device/device.h>
#include <intelblocks/pcr.h>
#include <soc/gpio.h>
#include <soc/pcr_ids.h>
#include <smbios.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define SERIAL_IO_PCR_GPPRVRW4 0x60C
static void mainboard_init(void *chip_info)
{
const struct pad_config *pads;
size_t num;
pads = variant_gpio_table(&num);
gpio_configure_pads(pads, num);
if (CONFIG(DRIVERS_INTEL_MIPI_CAMERA))
pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
const char *smbios_system_sku(void)
{
static const char *sku_str = "sku2147483647"; /* sku{0-1} */
return sku_str;
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

12
src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <console/console.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include "board_id.h"
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
/* ToDo : Fill FSP-M spd related memory params */
}

37
src/mainboard/intel/elkhartlake_crb/smihandler.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <elog.h>
#include <intelblocks/smihandler.h>
#include <baseboard/ec.h>
void mainboard_smi_espi_handler(void)
{
if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)
{
if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
return 0;
}
void elog_gsmi_cb_mainboard_log_wake_source(void)
{
if (CONFIG(EC_GOOGLE_CHROMEEC))
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
}

3
src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc Normal file
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## SPDX-License-Identifier: GPL-2.0-only
SPD_SOURCES = empty # 0b000

32
src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex Normal file
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

16
src/mainboard/intel/elkhartlake_crb/spd/spd.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#include <stdint.h>
#define RCOMP_TARGET_PARAMS 0x5
void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
#endif

67
src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __BASEBOARD_EC_H__
#define __BASEBOARD_EC_H__
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/*
* EC can wake from S3 with lid or power button or key press or
* mode change event.
*/
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
/*
* ACPI related definitions for ASL code.
*/
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
/* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
#endif /* __BASEBOARD_EC_H__ */

15
src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __BASEBOARD_GPIO_H__
#define __BASEBOARD_GPIO_H__
#include <soc/gpe.h>
#include <soc/gpio.h>
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
#endif /* __BASEBOARD_GPIO_H__ */

20
src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h>
#include <soc/meminit.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* The following 2 functions return the gpio table and fill in the number
* of entries for each table. */
const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
/* This function returns SPD related FSP-M mainboard configs */
const struct mb_cfg *variant_memcfg_config(uint8_t board_id);
#endif /*__BASEBOARD_VARIANTS_H__ */

5
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c

304
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb Normal file
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chip soc/intel/elkhartlake
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on
chip drivers/intel/dptf
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)"
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)"
register "controls.power_limits.pl1" = "{
.min_power = 3000,
.max_power = 6000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 20000,
.max_power = 20000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 1000,}"
device generic 0 on end
end
end # SA Thermal device
device pci 05.0 on
chip drivers/intel/mipi_camera
register "acpi_uid" = "0x50000"
register "acpi_name" = ""IPU0""
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "2"
register "cio2_lanes_used" = "{2,2}"
register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1""
register "cio2_prt[0]" = "0"
register "cio2_prt[1]" = "2"
device generic 0 on end
end
end
device pci 12.0 off end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB3/2 Type-A Left Lower""
register "type" = "UPC_TYPE_A"
device usb 2.0 on end
end
chip drivers/usb/acpi
register "desc" = ""WWAN""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.1 on end
end
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB C Connector 1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device usb 2.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB C Connector 2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device usb 2.4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB C Connector 3""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device usb 2.5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB C Connector 4""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device usb 2.6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3/2 Type-A Left Upper""
register "type" = "UPC_TYPE_A"
device usb 2.7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3/2 Type-A Left Lower""
register "type" = "UPC_TYPE_A"
device usb 3.0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3/2 Type-A Left Upper""
register "type" = "UPC_TYPE_A"
device usb 3.1 on end
end
chip drivers/usb/acpi
register "desc" = ""WLAN""
register "type" = "UPC_TYPE_INTERNAL"
device usb 3.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Port Unused1""
register "type" = "UPC_TYPE_INTERNAL"
device usb 3.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Port Unused2""
register "type" = "UPC_TYPE_INTERNAL"
device usb 3.4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Port Unused3""
register "type" = "UPC_TYPE_INTERNAL"
device usb 3.5 on end
end
end
end
end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 off end # PMC SRAM
device pci 14.3 on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end # CNVi wifi
device pci 14.5 on end # SDCard
device pci 15.0 on
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
register "imon_slot_no" = "5"
register "uid" = "0"
register "desc" = ""RIGHT SPEAKER AMP""
register "name" = ""MAXR""
device i2c 31 on end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "6"
register "imon_slot_no" = "7"
register "uid" = "1"
register "desc" = ""LEFT SPEAKER AMP""
register "name" = ""MAXL""
device i2c 32 on end
end
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "500"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end # I2C #0 Audio
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 off end # SATA
device pci 19.0 on # I2C #4 Cam 0
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI2740""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM0""
register "chip_name" = ""Ov 2740 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "has_power_resource" = "1"
register "ssdb.lanes_used" = "2"
register "num_freq_entries" = "1"
register "link_freq[0]" = "360000000"
register "remote_name" = ""IPU0""
#Controls
register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset
register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power
#_ON
register "on_seq.ops_cnt" = "4"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
#_OFF
register "off_seq.ops_cnt" = "3"
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
device i2c 10 on end
end
end
device pci 19.1 on # I2C #5 Cam 1 and VCM
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI5675""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM1""
register "chip_name" = ""Ov 5675 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "ssdb.lanes_used" = "2"
register "ssdb.link_used" = "1"
register "ssdb.vcm_type" = "0x0C"
register "vcm_name" = ""VCM0""
register "num_freq_entries" = "1"
register "link_freq[0]" = "DEFAULT_LINK_FREQ"
register "remote_name" = ""IPU0""
register "has_power_resource" = "1"
#Controls
register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable
register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset
#_ON
register "on_seq.ops_cnt" = "4"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
#_OFF
register "off_seq.ops_cnt" = "3"
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
device i2c 36 on end
end
chip drivers/intel/mipi_camera
register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
register "acpi_uid" = "3"
register "acpi_name" = ""VCM0""
register "chip_name" = ""DW AF DAC""
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC""
register "vcm_compat" = ""dongwoon,dw9714""
register "ssdb.lanes_used" = "2"
register "num_freq_entries" = "1"
register "link_freq[0]" = "DEFAULT_LINK_FREQ"
register "remote_name" = ""IPU0""
device i2c 0C on end
end
end
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 on end # PCI Express Port 2 - WLAN
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5 - NVMe
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)"
device spi 0 on end
end
end # GSPI #1
device pci 1f.0 on end # eSPI Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end
end

37
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c Normal file
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@ -0,0 +1,37 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* ToDo: Fill gpio configurations */
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* ToDo: Fill early gpio configurations */
};
const struct pad_config *variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
};
const struct cros_gpio *variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}

16
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
/* ToDo : Fill EHL related memory configs */
const struct mb_cfg *variant_memcfg_config(uint8_t board_id)
{
/* ToDo : Fill EHL related memory configs */
die("unsupported board id : 0x%x\n", board_id);
}