From d2e278df334f85a2ec2001fe2c477ceb186a565b Mon Sep 17 00:00:00 2001 From: Julian Schroeder Date: Thu, 20 Jan 2022 15:09:52 -0600 Subject: [PATCH] soc/amd/common/fsp: check fsp image revision Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/common/fsp/fsp_validate.c | 41 ++++++++++++++++++++++-- src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 6 ++++ src/vendorcode/amd/fsp/picasso/FspmUpd.h | 5 +++ src/vendorcode/amd/fsp/sabrina/FspmUpd.h | 5 +++ 4 files changed, 55 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/fsp/fsp_validate.c b/src/soc/amd/common/fsp/fsp_validate.c index 4d6a8f72bc..d9ff5026b3 100644 --- a/src/soc/amd/common/fsp/fsp_validate.c +++ b/src/soc/amd/common/fsp/fsp_validate.c @@ -4,12 +4,49 @@ #include #include +struct amd_image_revision { + uint8_t build; + uint8_t revision; + uint8_t minor; + uint8_t major; +} __packed; + /* Validate the FSP-M header in romstage */ void soc_validate_fspm_header(const struct fsp_header *hdr) { + struct amd_image_revision *rev; + + rev = (struct amd_image_revision *) &(hdr->image_revision); + /* Check if the image fits into the reserved memory region */ if (hdr->image_size > CONFIG_FSP_M_SIZE) - die("The FSP-M binary is %u bytes larger than the memory region allocated for " - "it. Increase FSP_M_SIZE to make it fit.\n", + die("The FSP-M binary is %u bytes larger than the memory region" + " allocated for it. Increase FSP_M_SIZE to make it fit.\n", hdr->image_size - CONFIG_FSP_M_SIZE); + + /* a coding bug on the AMD FSP side makes this value 1 in + older versions of the FSP.*/ + if (hdr->image_revision == 1) { + printk(BIOS_ERR, "No AMD FSP image revision information available\n"); + return; + } + + printk(BIOS_INFO, "FSP major = %d\n", rev->major); + printk(BIOS_INFO, "FSP minor = %d\n", rev->minor); + printk(BIOS_INFO, "FSP revision = %d\n", rev->revision); + printk(BIOS_INFO, "FSP build = %d\n", rev->build); + + if ((rev->major != IMAGE_REVISION_MAJOR_VERSION) || + (rev->minor != IMAGE_REVISION_MINOR_VERSION)) { + printk(BIOS_WARNING, "FSP binary and SOC FSP header file don't match.\n"); + printk(BIOS_WARNING, "include file ImageRevisionMajorVersion=%d\n", + IMAGE_REVISION_MAJOR_VERSION); + printk(BIOS_WARNING, "include file ImageRevisionMinorVersion=%d\n", + IMAGE_REVISION_MINOR_VERSION); + printk(BIOS_WARNING, "Please update FspmUpd.h based on the corresponding FSP" + " build's FspmUpd.h\n"); + } + + if (rev->major != IMAGE_REVISION_MAJOR_VERSION) + die("IMAGE_REVISION_MAJOR_VERSION mismatch, halting\nGoodbye now\n"); } diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 7cee318126..38aa36cb07 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -114,4 +114,10 @@ typedef struct __packed { /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; } FSPM_UPD; +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x05 +#define IMAGE_REVISION_BUILD_NUMBER 0x00 + + #endif diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index 28b000bb13..abb61acb4c 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -79,4 +79,9 @@ typedef struct __packed { /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; } FSPM_UPD; +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x02 +#define IMAGE_REVISION_BUILD_NUMBER 0x04 + #endif diff --git a/src/vendorcode/amd/fsp/sabrina/FspmUpd.h b/src/vendorcode/amd/fsp/sabrina/FspmUpd.h index f21ca42169..f42ed4365c 100644 --- a/src/vendorcode/amd/fsp/sabrina/FspmUpd.h +++ b/src/vendorcode/amd/fsp/sabrina/FspmUpd.h @@ -107,4 +107,9 @@ typedef struct __packed { /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; } FSPM_UPD; +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x05 +#define IMAGE_REVISION_BUILD_NUMBER 0x00 + #endif