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southbridge/amd: add support for Bolton FCH 

The Bolton FCH needs different firmware files than the Hudson FCH.

A small patch to vendorcode is probably needed to make the XHCI controller work.

XHCI_DEVID in pci_devs.h is probably wrong for Hudson.

Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/9623
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Felix Held 2015-05-31 20:28:17 +02:00 committed by Martin Roth
parent e536a4d916
commit d2e8f6ad33
6 changed files with 27 additions and 7 deletions
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1
src/southbridge/amd/agesa/Makefile.inc
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@ -13,5 +13,6 @@
# GNU General Public License for more details.
#
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += hudson
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson

13
src/southbridge/amd/agesa/hudson/Kconfig
View File

@ -13,6 +13,12 @@
## GNU General Public License for more details.
##
config SOUTHBRIDGE_AMD_AGESA_BOLTON
bool
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
config SOUTHBRIDGE_AMD_AGESA_HUDSON
bool
select IOAPIC
@ -25,7 +31,7 @@ config SOUTHBRIDGE_AMD_AGESA_YANGTZE
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
@ -70,18 +76,21 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename"
default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE
string "GEC firmware path and filename"
default "3rdparty/blobs/southbridge/amd/bolton/gec.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_GEC_FWM
@ -204,7 +213,7 @@ config ACPI_ENABLE_THERMAL_ZONE
bool
default y
endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
endif # SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
if SOUTHBRIDGE_AMD_AGESA_YANGTZE
config AZ_PIN

6
src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
View File

@ -21,7 +21,7 @@
* into the FCH PCI_INTR 0xC00/0xC01 interrupt
* routing table
*/
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define FCH_INT_TABLE_SIZE 0x54
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#define FCH_INT_TABLE_SIZE 0x42
@ -51,7 +51,7 @@
#define PIRQ_FC 0x14 /* FC */
#define PIRQ_GEC 0x15 /* GEC */
#define PIRQ_PMON 0x16 /* Performance Monitor */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#define PIRQ_SD 0x17 /* SD */
#endif
#define PIRQ_IMC0 0x20 /* IMC INT0 */
@ -71,6 +71,8 @@
#define PIRQ_SATA 0x41 /* SATA 11h.0 */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define PIRQ_SD 0x42 /* SD 14h.7 */
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define PIRQ_GPP0 0x50 /* GPP INT 0 */
#define PIRQ_GPP1 0x51 /* GPP INT 1 */
#define PIRQ_GPP2 0x52 /* GPP INT 2 */

2
src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
View File

@ -16,7 +16,7 @@
#ifndef AMD_PCI_INT_TYPES_H
#define AMD_PCI_INT_TYPES_H
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
const char * intr_types[] = {
[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",

11
src/southbridge/amd/agesa/hudson/pci_devs.h
View File

@ -24,6 +24,13 @@
#define XHCI_DEVID 0x7814
#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON)
#define XHCI2_DEV 0x10
#define XHCI2_FUNC 1
#define XHCI2_DEVID 0x7814
#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
#endif
/* SATA */
#define SATA_DEV 0x11
#define SATA_FUNC 0
@ -66,7 +73,7 @@
#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
/* IDE */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define IDE_DEV 0x14
#define IDE_FUNC 1
# define IDE_DEVID 0x780C
@ -99,7 +106,7 @@
#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
/* PCIe Ports */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define SB_PCIE_DEV 0x15
#define SB_PCIE_PORT1_FUNC 0
#define SB_PCIE_PORT2_FUNC 1

1
src/southbridge/amd/common/Makefile.inc
View File

@ -1,6 +1,7 @@
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c