mainboard/google/reef: Enable lpss s0ix

This setting enables lpss to power gate in S0ix.

BUG=chrome-os-partner:53876

Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/reef/variants/baseboard/devicetree.cb

@@ -50,6 +50,9 @@ chip soc/intel/apollolake
 	register "hdaudio_pwr_gate_enable" = "1"
 	register "hdaudio_bios_config_lockdown" = "1"
 
+	# Enable lpss s0ix
+	register "lpss_s0ix_enable" = "1"
+
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route, i.e., if this route changes then the affected GPE