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mainboard/google/reef: Enable lpss s0ix 

This setting enables lpss to power gate in S0ix.

BUG=chrome-os-partner:53876

Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Venkateswarlu Vinjamuri 2016-09-08 16:11:27 -07:00 committed by Martin Roth
parent 6584973bdc
commit d2e92e461d
1 changed files with 3 additions and 0 deletions
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src/mainboard/google/reef/variants/baseboard/devicetree.cb
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@ -50,6 +50,9 @@ chip soc/intel/apollolake
register "hdaudio_pwr_gate_enable" = "1" register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1" register "hdaudio_bios_config_lockdown" = "1"
# Enable lpss s0ix
register "lpss_s0ix_enable" = "1"
# GPE configuration # GPE configuration
# Note that GPE events called out in ASL code rely on this # Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE # route, i.e., if this route changes then the affected GPE