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mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixes 

Use lowercase for hex constants and align some comments.

Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-01-01 19:19:47 +01:00 committed by Nico Huber
parent 7a61c6c398
commit d2f3afcc17
3 changed files with 17 additions and 17 deletions
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14
src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
View File

@ -20,15 +20,15 @@ chip northbridge/intel/x4x # Northbridge
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
chip cpu/intel/model_1067x # CPU
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller
device pci 2.1 off end # Integrated graphics controller 2
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller
device pci 2.1 off end # Integrated graphics controller 2
device pci 3.0 off end # ME
device pci 3.1 off end # ME
device pci 3.2 off end # ME
@ -43,7 +43,7 @@ chip northbridge/intel/x4x # Northbridge
register "sata_traffic_monitor" = "0"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
register "pcie_slot_implemented" = "0x31"
register "gen1_dec" = "0x00000295"
register "gen2_dec" = "0x001c4701"

14
src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
View File

@ -20,15 +20,15 @@ chip northbridge/intel/x4x # Northbridge
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
chip cpu/intel/model_1067x # CPU
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller
device pci 2.1 off end # Integrated graphics controller 2
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller
device pci 2.1 off end # Integrated graphics controller 2
device pci 3.0 off end # ME
device pci 3.1 off end # ME
device pci 3.2 off end # ME
@ -43,7 +43,7 @@ chip northbridge/intel/x4x # Northbridge
register "sata_traffic_monitor" = "0"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
register "pcie_slot_implemented" = "0x31"
register "gen1_dec" = "0x00000295"
register "gen2_dec" = "0x001c4701"

6
src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
View File

@ -20,8 +20,8 @@ chip northbridge/intel/x4x # Northbridge
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
chip cpu/intel/model_1067x # CPU
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
@ -43,7 +43,7 @@ chip northbridge/intel/x4x # Northbridge
register "sata_traffic_monitor" = "0"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
register "pcie_slot_implemented" = "0x31"
register "gen1_dec" = "0x00000295"
register "gen2_dec" = "0x001c4701"