soc/intel: replace dt option PmTimerDisabled by Kconfig
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -52,4 +52,8 @@ config POST_DEVICE
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config UART_FOR_CONSOLE
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default 2
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# PM Timer Disabled, saves power
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config USE_PM_ACPI_TIMER
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default n
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endif
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@ -26,10 +26,6 @@ chip soc/intel/tigerlake
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.tdp_pl2_override = 40,
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}"
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# Finalize (soc/intel/tigerlake/finalize.c)
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# PM Timer Disabled, saves power
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register "PmTimerDisabled" = "1"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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@ -53,4 +53,8 @@ config POST_DEVICE
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config UART_FOR_CONSOLE
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default 2
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# PM Timer Disabled, saves power
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config USE_PM_ACPI_TIMER
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default n
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endif
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@ -26,10 +26,6 @@ chip soc/intel/tigerlake
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.tdp_pl2_override = 51,
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}"
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# Finalize (soc/intel/tigerlake/finalize.c)
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# PM Timer Disabled, saves power
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register "PmTimerDisabled" = "1"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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@ -52,4 +52,8 @@ config POST_DEVICE
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config UART_FOR_CONSOLE
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default 2
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# PM Timer Disabled, saves power
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config USE_PM_ACPI_TIMER
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default n
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endif
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@ -26,10 +26,6 @@ chip soc/intel/tigerlake
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.tdp_pl2_override = 30,
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}"
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# Finalize (soc/intel/tigerlake/finalize.c)
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# PM Timer Disabled, saves power
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register "PmTimerDisabled" = "1"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP_AP_WORK
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select MICROCODE_BLOB_UNDISCLOSED
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select PLATFORM_USES_FSP2_2
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select PM_ACPI_TIMER_OPTIONAL
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select PMC_LOW_POWER_MODE_PROGRAM
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select SOC_INTEL_COMMON
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@ -286,7 +286,7 @@ struct soc_intel_alderlake_config {
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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uint8_t PmTimerDisabled;
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/*
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* SerialIO device mode selection:
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* PchSerialIoDisabled,
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@ -50,7 +50,7 @@ static void pch_handle_sideband(config_t *config)
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static void pch_finalize(void)
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{
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config_t *config;
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config_t *config = config_of_soc();
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/* TCO Lock down */
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tco_lockdown();
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@ -58,13 +58,12 @@ static void pch_finalize(void)
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/* TODO: Add Thermal Configuration */
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/*
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* Disable ACPI PM timer based on dt policy
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* Disable ACPI PM timer based on Kconfig
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*/
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config = config_of_soc();
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if (config->PmTimerDisabled)
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if (!CONFIG(USE_PM_ACPI_TIMER))
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pmc_disable_acpi_timer();
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pch_handle_sideband(config);
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@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP_AP_WORK
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select MICROCODE_BLOB_UNDISCLOSED
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select PLATFORM_USES_FSP2_1
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select PM_ACPI_TIMER_OPTIONAL
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select PMC_LOW_POWER_MODE_PROGRAM
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select SOC_INTEL_COMMON
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@ -236,8 +236,6 @@ struct soc_intel_elkhartlake_config {
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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uint8_t PmTimerDisabled;
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/*
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* SerialIO device mode selection:
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* PchSerialIoDisabled,
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@ -24,26 +24,18 @@
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static void pch_finalize(void)
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{
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config_t *config;
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/* TCO Lock down */
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tco_lockdown();
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/* TODO: Add Thermal Configuration */
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/*
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* Disable ACPI PM timer based on dt policy
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* Disable ACPI PM timer based on Kconfig
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*
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* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
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* just required to get to chip config. PCH_DEV_PMC is hidden by this
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* point and hence removed from the root bus. pcidev_path_on_root thus
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* returns NULL for PCH_DEV_PMC device.
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*/
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config = config_of_soc();
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if (config->PmTimerDisabled)
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if (!CONFIG(USE_PM_ACPI_TIMER))
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pmc_disable_acpi_timer();
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pmc_clear_pmcon_sts();
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@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP_AP_WORK
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select MICROCODE_BLOB_UNDISCLOSED
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select PLATFORM_USES_FSP2_1
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select PM_ACPI_TIMER_OPTIONAL
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select PMC_LOW_POWER_MODE_PROGRAM
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select CPU_INTEL_COMMON
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@ -144,8 +144,6 @@ struct soc_intel_icelake_config {
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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uint8_t PmTimerDisabled;
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/*
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* SerialIO device mode selection:
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* PchSerialIoDisabled,
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@ -40,7 +40,7 @@ static void pch_handle_sideband(config_t *config)
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static void pch_finalize(void)
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{
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config_t *config;
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config_t *config = config_of_soc();
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/* TCO Lock down */
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tco_lockdown();
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@ -55,18 +55,12 @@ static void pch_finalize(void)
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pch_thermal_configuration();
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/*
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* Disable ACPI PM timer based on dt policy
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* Disable ACPI PM timer based on Kconfig
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*
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* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
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* just required to get to chip config. PCH_DEV_PMC is hidden by this
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* point and hence removed from the root bus. pcidev_path_on_root thus
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* returns NULL for PCH_DEV_PMC device.
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*/
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config = config_of_soc();
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if (config->PmTimerDisabled)
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if (!CONFIG(USE_PM_ACPI_TIMER))
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pmc_disable_acpi_timer();
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pch_handle_sideband(config);
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@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP_AP_WORK
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select MICROCODE_BLOB_UNDISCLOSED
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select PLATFORM_USES_FSP2_2
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select PM_ACPI_TIMER_OPTIONAL
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select PMC_LOW_POWER_MODE_PROGRAM
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select SOC_INTEL_COMMON
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@ -152,8 +152,6 @@ struct soc_intel_jasperlake_config {
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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uint8_t PmTimerDisabled;
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/*
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* SerialIO device mode selection:
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* PchSerialIoDisabled,
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@ -44,7 +44,7 @@ static void pch_finalize(void)
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{
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uint32_t reg32;
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uint8_t *pmcbase;
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config_t *config;
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config_t *config = config_of_soc();
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/* TCO Lock down */
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tco_lockdown();
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@ -52,18 +52,12 @@ static void pch_finalize(void)
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/* TODO: Add Thermal Configuration */
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/*
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* Disable ACPI PM timer based on dt policy
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* Disable ACPI PM timer based on Kconfig
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*
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* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
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* just required to get to chip config. PCH_DEV_PMC is hidden by this
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* point and hence removed from the root bus. pcidev_path_on_root thus
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* returns NULL for PCH_DEV_PMC device.
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*/
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config = config_of_soc();
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if (config->PmTimerDisabled)
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if (!CONFIG(USE_PM_ACPI_TIMER))
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pmc_disable_acpi_timer();
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pmcbase = pmc_mmio_regs();
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@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
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select MRC_SETTINGS_PROTECT
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select PARALLEL_MP_AP_WORK
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select PLATFORM_USES_FSP2_2
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select PM_ACPI_TIMER_OPTIONAL
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select PMC_LOW_POWER_MODE_PROGRAM
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select SOC_INTEL_COMMON
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@ -289,7 +289,7 @@ struct soc_intel_tigerlake_config {
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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uint8_t PmTimerDisabled;
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/*
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* SerialIO device mode selection:
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* PchSerialIoDisabled,
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@ -30,8 +30,6 @@
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static void pch_finalize(void)
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{
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config_t *config;
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/* TCO Lock down */
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tco_lockdown();
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@ -42,14 +40,8 @@ static void pch_finalize(void)
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*
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* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
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* just required to get to chip config. PCH_DEV_PMC is hidden by this
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* point and hence removed from the root bus. pcidev_path_on_root thus
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* returns NULL for PCH_DEV_PMC device.
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*/
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config = config_of_soc();
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if (config->PmTimerDisabled)
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if (!CONFIG(USE_PM_ACPI_TIMER))
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pmc_disable_acpi_timer();
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pmc_clear_pmcon_sts();
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