soc/intel: replace dt option PmTimerDisabled by Kconfig

Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.

A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.

Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2021-09-27 19:26:20 +02:00
parent 87e0b5b1d7
commit d2fadda52a
21 changed files with 31 additions and 61 deletions

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@ -52,4 +52,8 @@ config POST_DEVICE
config UART_FOR_CONSOLE
default 2
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

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@ -26,10 +26,6 @@ chip soc/intel/tigerlake
.tdp_pl2_override = 40,
}"
# Finalize (soc/intel/tigerlake/finalize.c)
# PM Timer Disabled, saves power
register "PmTimerDisabled" = "1"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"

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@ -53,4 +53,8 @@ config POST_DEVICE
config UART_FOR_CONSOLE
default 2
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

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@ -26,10 +26,6 @@ chip soc/intel/tigerlake
.tdp_pl2_override = 51,
}"
# Finalize (soc/intel/tigerlake/finalize.c)
# PM Timer Disabled, saves power
register "PmTimerDisabled" = "1"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"

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@ -52,4 +52,8 @@ config POST_DEVICE
config UART_FOR_CONSOLE
default 2
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

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@ -26,10 +26,6 @@ chip soc/intel/tigerlake
.tdp_pl2_override = 30,
}"
# Finalize (soc/intel/tigerlake/finalize.c)
# PM Timer Disabled, saves power
register "PmTimerDisabled" = "1"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"

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@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2
select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
select PMC_LOW_POWER_MODE_PROGRAM
select SOC_INTEL_COMMON

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@ -286,7 +286,7 @@ struct soc_intel_alderlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,

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@ -50,7 +50,7 @@ static void pch_handle_sideband(config_t *config)
static void pch_finalize(void)
{
config_t *config;
config_t *config = config_of_soc();
/* TCO Lock down */
tco_lockdown();
@ -58,13 +58,12 @@ static void pch_finalize(void)
/* TODO: Add Thermal Configuration */
/*
* Disable ACPI PM timer based on dt policy
* Disable ACPI PM timer based on Kconfig
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*/
config = config_of_soc();
if (config->PmTimerDisabled)
if (!CONFIG(USE_PM_ACPI_TIMER))
pmc_disable_acpi_timer();
pch_handle_sideband(config);

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@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1
select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
select PMC_LOW_POWER_MODE_PROGRAM
select SOC_INTEL_COMMON

View File

@ -236,8 +236,6 @@ struct soc_intel_elkhartlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,

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@ -24,26 +24,18 @@
static void pch_finalize(void)
{
config_t *config;
/* TCO Lock down */
tco_lockdown();
/* TODO: Add Thermal Configuration */
/*
* Disable ACPI PM timer based on dt policy
* Disable ACPI PM timer based on Kconfig
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*
* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
* just required to get to chip config. PCH_DEV_PMC is hidden by this
* point and hence removed from the root bus. pcidev_path_on_root thus
* returns NULL for PCH_DEV_PMC device.
*/
config = config_of_soc();
if (config->PmTimerDisabled)
if (!CONFIG(USE_PM_ACPI_TIMER))
pmc_disable_acpi_timer();
pmc_clear_pmcon_sts();

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@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1
select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
select PMC_LOW_POWER_MODE_PROGRAM
select CPU_INTEL_COMMON

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@ -144,8 +144,6 @@ struct soc_intel_icelake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,

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@ -40,7 +40,7 @@ static void pch_handle_sideband(config_t *config)
static void pch_finalize(void)
{
config_t *config;
config_t *config = config_of_soc();
/* TCO Lock down */
tco_lockdown();
@ -55,18 +55,12 @@ static void pch_finalize(void)
pch_thermal_configuration();
/*
* Disable ACPI PM timer based on dt policy
* Disable ACPI PM timer based on Kconfig
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*
* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
* just required to get to chip config. PCH_DEV_PMC is hidden by this
* point and hence removed from the root bus. pcidev_path_on_root thus
* returns NULL for PCH_DEV_PMC device.
*/
config = config_of_soc();
if (config->PmTimerDisabled)
if (!CONFIG(USE_PM_ACPI_TIMER))
pmc_disable_acpi_timer();
pch_handle_sideband(config);

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@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2
select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
select PMC_LOW_POWER_MODE_PROGRAM
select SOC_INTEL_COMMON

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@ -152,8 +152,6 @@ struct soc_intel_jasperlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,

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@ -44,7 +44,7 @@ static void pch_finalize(void)
{
uint32_t reg32;
uint8_t *pmcbase;
config_t *config;
config_t *config = config_of_soc();
/* TCO Lock down */
tco_lockdown();
@ -52,18 +52,12 @@ static void pch_finalize(void)
/* TODO: Add Thermal Configuration */
/*
* Disable ACPI PM timer based on dt policy
* Disable ACPI PM timer based on Kconfig
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*
* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
* just required to get to chip config. PCH_DEV_PMC is hidden by this
* point and hence removed from the root bus. pcidev_path_on_root thus
* returns NULL for PCH_DEV_PMC device.
*/
config = config_of_soc();
if (config->PmTimerDisabled)
if (!CONFIG(USE_PM_ACPI_TIMER))
pmc_disable_acpi_timer();
pmcbase = pmc_mmio_regs();

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@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_2
select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
select PMC_LOW_POWER_MODE_PROGRAM
select SOC_INTEL_COMMON

View File

@ -289,7 +289,7 @@ struct soc_intel_tigerlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,

View File

@ -30,8 +30,6 @@
static void pch_finalize(void)
{
config_t *config;
/* TCO Lock down */
tco_lockdown();
@ -42,14 +40,8 @@ static void pch_finalize(void)
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*
* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
* just required to get to chip config. PCH_DEV_PMC is hidden by this
* point and hence removed from the root bus. pcidev_path_on_root thus
* returns NULL for PCH_DEV_PMC device.
*/
config = config_of_soc();
if (config->PmTimerDisabled)
if (!CONFIG(USE_PM_ACPI_TIMER))
pmc_disable_acpi_timer();
pmc_clear_pmcon_sts();