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src/vendorcode/amd/pi/00670F00: Remove IMC support 

Per AMD, the Integrated Micro Controller is not a supported feature of the
Stoney Ridge APU.  Systems are expected to implement an external EC for
desired features. Remove all stoney IMC files and functions from vendor code.

BUG=b:111780177
TEST=Build grunt and gardenia

Change-Id: I06e993fa498cc0978c1d037bc6001682407f7fac
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27652
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel 2018-07-26 14:28:19 -07:00 committed by Martin Roth
parent 7108107fa2
commit d30201feaf
4 changed files with 1 additions and 524 deletions
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188
src/vendorcode/amd/pi/00670F00/Lib/imc/HwmLateService.c
View File

@ -1,188 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMLATESERVICE_FILECODE
/**
* Table for Function Number
*
*
*
*
*/
STATIC UINT8 FunctionNumber[] =
{
Fun_81,
Fun_83,
Fun_85,
Fun_89,
};
/**
* Table for Max Thermal Zone
*
*
*
*
*/
UINT8 MaxZone[] =
{
4,
4,
4,
4,
};
/**
* Table for Max Register
*
*
*
*
*/
UINT8 MaxRegister[] =
{
MSG_REG9,
MSG_REGB,
MSG_REG9,
MSG_REGA,
};
/*-------------------------------------------------------------------------------
;Procedure: IsZoneFuncEnable
;
;Description: This routine will check every zone support function with BitMap from user define
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
STATIC BOOLEAN
IsZoneFuncEnable (
IN UINT16 Flag,
IN UINT8 func,
IN UINT8 Zone
)
{
return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
}
/*-------------------------------------------------------------------------------
;Procedure: FchECfancontrolservice
;
;Description: This routine service EC fan policy
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
VOID
FchECfancontrolservice (
IN VOID *FchDataPtr
)
{
UINT8 ZoneNum;
UINT8 FunNum;
UINT8 RegNum;
UINT8 *CurPoint;
UINT8 FunIndex;
BOOLEAN IsSendEcMsg;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if (!IsImcEnabled (StdHeader)) {
return; //IMC is not enabled
}
CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
if (IsSendEcMsg) {
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
CurPoint += 1;
}
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
WaitForEcLDN9MailboxCmdAck (StdHeader);
} else {
CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
}
}
}
CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0;
for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
if (IsSendEcMsg) {
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
if (RegNum == MSG_REG2) {
*CurPoint &= 0xFE;
}
WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
CurPoint += 1;
}
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
WaitForEcLDN9MailboxCmdAck (StdHeader);
} else {
CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
}
}
}
}

312
src/vendorcode/amd/pi/00670F00/Lib/imc/ImcLib.c
View File

@ -1,312 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH IMC lib
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 87213 $ @e \$Date: 2013-01-30 15:37:54 -0600 (Wed, 30 Jan 2013) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
/**
* WriteECmsg
*
*
*
* @param[in] Address - Address
* @param[in] OpFlag - Access width
* @param[in] *Value - Out Value pointer
* @param[in] StdHeader
*
*/
VOID
WriteECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Index;
ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
OpFlag = (OpFlag & 0x7f) - 1;
if (OpFlag == 0x02) {
OpFlag = 0x03;
}
for (Index = 0; Index <= OpFlag; Index++) {
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader);
Address++;
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoWrite (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader);
}
}
/**
* ReadECmsg
*
*
*
* @param[in] Address - Address
* @param[in] OpFlag - Access width
* @param[out] *Value - Out Value pointer
* @param[in] StdHeader
*
*/
VOID
ReadECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
OUT VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Index;
ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
OpFlag = (OpFlag & 0x7f) - 1;
if (OpFlag == 0x02) {
OpFlag = 0x03;
}
for (Index = 0; Index <= OpFlag; Index++) {
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader);
Address++;
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoRead (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader);
}
}
/**
* WaitForEcLDN9MailboxCmdAck
*
*
* @param[in] StdHeader
*
*/
VOID
WaitForEcLDN9MailboxCmdAck (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Msgdata;
UINT16 Delaytime;
Msgdata = 0;
for (Delaytime = 0; Delaytime < 0xFFFF; Delaytime++) {
ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
if ( Msgdata == 0xfa) {
break;
}
FchStall (5, StdHeader); /// Wait for 1ms
}
}
/**
* ImcSleep - IMC Sleep.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcSleep (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0xB4;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x96;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
/**
* SoftwareDisableImc - Software disable IMC strap
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SoftwareDisableImc (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT8 PortStatusByte;
UINT32 AbValue;
UINT32 ABStrapOverrideReg;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
ReadPmio (0xBF, AccessWidth8, &ValueByte, StdHeader);
ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
ABStrapOverrideReg = AbValue;
ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap
WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84), AccessWidth32, &ABStrapOverrideReg);
ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte |= BIT1;
WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte = 06;
LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
FchStall (0xffffffff, StdHeader);
}
/**
* ImcDisableSurebootTimer - IMC Disable Sureboot Timer.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcDisableSurebootTimer (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
ImcWakeup (FchDataPtr);
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x94;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
ImcSleep (FchDataPtr);
}
/**
* ImcWakeup - IMC Wakeup.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcWakeup (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0xB5;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x96;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
/**
* ImcIdle - IMC Idle.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcIdle (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x98;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}

5
src/vendorcode/amd/pi/00670F00/Makefile.inc
View File

@ -94,11 +94,6 @@ ifeq ($(CONFIG_VENDORCODE_FULL_SUPPORT),y)
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])
endif
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS])
ifeq ($(CONFIG_STONEYRIDGE_IMC_FWM),y)
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Lib/imc/*.c)
agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c
agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c
endif
classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa

20
src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h
View File

@ -62,7 +62,6 @@ VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET
VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);
VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
@ -183,18 +182,14 @@ VOID FchECfancontrolservice (IN VOID* FchDataPtr);
///
/// Fch Imc Routines
/// Fch EC Routines
///
/// Pei Phase
///
VOID FchInitResetImc (IN VOID *FchDataPtr);
VOID FchInitResetEc (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvImc (IN VOID *FchDataPtr);
VOID FchInitMidImc (IN VOID *FchDataPtr);
VOID FchInitLateImc (IN VOID *FchDataPtr);
VOID FchInitEnvEc (IN VOID *FchDataPtr);
VOID FchInitMidEc (IN VOID *FchDataPtr);
VOID FchInitLateEc (IN VOID *FchDataPtr);
@ -210,17 +205,6 @@ VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CO
VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ImcSleep (IN VOID *FchDataPtr);
VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
VOID ImcWakeup (IN VOID *FchDataPtr);
VOID ImcIdle (IN VOID *FchDataPtr);
BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
VOID ImcCrashReset (IN VOID *FchDataPtr);
VOID SoftwareDisableImc (IN VOID *FchDataPtr);
///
/// Fch Ir Routines
///
@ -428,6 +412,4 @@ RetrieveDataBlockFromInitReset (
IN FCH_DATA_BLOCK *FchParams
);
#endif