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i945: make PCIe link wait sensible 

Waiting for (a & 4) == 3 to become true proves futile
unless you're searching for defective hardware or
neutrino impact.

While I'm not 100% sure that this is the actual intent
(no data-sheets at hand, and the public ones are unhelpful
as usual), it's the likely correct version and it's also
boot-tested on intel/d945gclf.

While at it, replace register number with the name found
in the public datasheet.

Change-Id: I4b87001967a2013e0089806e8cd606d5ee81b0d9
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6575
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Patrick Georgi 2014-08-10 15:19:45 +02:00 committed by Patrick Georgi
parent 24d875bddc
commit d3060edce2
2 changed files with 6 additions and 5 deletions
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10
src/northbridge/intel/i945/early_init.c
View File

@ -588,7 +588,7 @@ static void i945_setup_pci_express_x16(void)
/* Wait for training to succeed */ /* Wait for training to succeed */
printk(BIOS_DEBUG, "PCIe link training ..."); printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff; timeout = 0x7ffff;
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ;
reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) { if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@ -599,10 +599,10 @@ static void i945_setup_pci_express_x16(void)
printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
reg32 &= ~(0xf << 1); reg32 &= ~(0xf << 1);
reg32 |=1; reg32 |=1;
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
@ -613,7 +613,7 @@ static void i945_setup_pci_express_x16(void)
printk(BIOS_DEBUG, "PCIe link training ..."); printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff; timeout = 0x7ffff;
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ;
reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) { if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@ -787,7 +787,7 @@ disable_pciexpress_x16_link:
printk(BIOS_DEBUG, "Wait for link to enter detect state... "); printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff; timeout = 0x7fffff;
for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
(reg32 & 0x000f0000) && --timeout;) ; (reg32 & 0x000f0000) && --timeout;) ;
if (!timeout) if (!timeout)
printk(BIOS_DEBUG, "timeout!\n"); printk(BIOS_DEBUG, "timeout!\n");

1
src/northbridge/intel/i945/i945.h
View File

@ -83,6 +83,7 @@
/* Device 0:1.0 PCI configuration space (PCI Express) */ /* Device 0:1.0 PCI configuration space (PCI Express) */
#define BCTRL1 0x3e /* 16bit */ #define BCTRL1 0x3e /* 16bit */
#define PEGSTS 0x214 /* 32bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */ /* Device 0:2.0 PCI configuration space (Graphics Device) */