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cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's 

Intel pineview has the same alternative SMRR MSR and
IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for
that before enabling this feature.

This also exposes a function to fetch whether alternative SMRR MSR's
ought to be used.

Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30868
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-01-12 00:27:18 +01:00
parent 2c64a806ee
commit d30894b835
2 changed files with 23 additions and 7 deletions
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2
src/cpu/intel/smm/gen1/smi.h
View File

@ -19,3 +19,5 @@ u32 northbridge_get_tseg_base(void);
u32 northbridge_get_tseg_size(void); u32 northbridge_get_tseg_size(void);
int cpu_get_apic_id_map(int *apic_id_map); int cpu_get_apic_id_map(int *apic_id_map);
void northbridge_write_smram(u8 smram); void northbridge_write_smram(u8 smram);
bool cpu_has_alternative_smrr(void);

28
src/cpu/intel/smm/gen1/smmrelocate.c
View File

@ -56,17 +56,31 @@ struct smm_relocation_params {
static struct smm_relocation_params smm_reloc_params; static struct smm_relocation_params smm_reloc_params;
static void *default_smm_area = NULL; static void *default_smm_area = NULL;
static void write_smrr(struct smm_relocation_params *relo_params) /* On model_6fx, model_1067x and model_106cx SMRR functions slightly
differently. The MSR are at different location from the rest
and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
bool cpu_has_alternative_smrr(void)
{ {
struct cpuinfo_x86 c; struct cpuinfo_x86 c;
get_fms(&c, cpuid_eax(1));
if (c.x86 != 6)
return false;
switch (c.x86_model) {
case 0xf:
case 0x17: /* core2 */
case 0x1c: /* Bonnell */
return true;
default:
return false;
}
}
static void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo); relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
/* Both model_6fx and model_1067x SMRR function slightly differently
from the rest. The MSR are at different location from the rest if (cpu_has_alternative_smrr()) {
and need to be explicitly enabled. */
get_fms(&c, cpuid_eax(1));
if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) {
msr_t msr; msr_t msr;
msr = rdmsr(IA32_FEATURE_CONTROL); msr = rdmsr(IA32_FEATURE_CONTROL);
/* SMRR enabled and feature locked */ /* SMRR enabled and feature locked */
@ -171,7 +185,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
/* On model_6fx and model_1067x bits [0:11] on smrr_base /* On model_6fx and model_1067x bits [0:11] on smrr_base
are reserved */ are reserved */
get_fms(&c, cpuid_eax(1)); get_fms(&c, cpuid_eax(1));
if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) if (cpu_has_alternative_smrr())
params->smrr_base.lo = (params->smram_base & rmask); params->smrr_base.lo = (params->smram_base & rmask);
else else
params->smrr_base.lo = (params->smram_base & rmask) params->smrr_base.lo = (params->smram_base & rmask)