mb/inventec: Add Intel SPR server board Inventec Transformers
CPU: - 2 SPR sockets - 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU - Up to 32 DDR5 DIMM - 1 Gbase-T NIC port - 1 USB3.0 type A, 1 USB2.0 connector - 1 VGA connector BMC: - ASPEED AST2600 BMC - 1 DDR4 8Gb memory - 1 8GB eMMC Test: The board boots to Linux 4.19.6 with all 192 cores available. Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com> Reviewed-by: Annie Chen <chen.annieet@inventec.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Annie Chen
Felix Singer
parent
77b71cf9d7
commit
d31cbc74d1
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@ -418,7 +418,10 @@ M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
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S: Maintained
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F: src/mainboard/intel/harcuvar/
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INVENTEC MAINBOARDS
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M: Annie Chen <Chen.AnnieET@inventec.com>
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S: Maintained
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F: src/mainboard/inventec/
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JETWAY MAINBOARDS
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S: Orphan
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@ -0,0 +1,16 @@
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# Inventec Transformers coreboot is modified from Intel ArcherCity CRB
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# Inventec Transformers is a dual socket CRB based on Intel.
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# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
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#
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# Type this in coreboot root directory to get a working .config:
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# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
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CONFIG_VENDOR_INVENTEC=y
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CONFIG_BOARD_INVENTEC_TRANSFORMERS=y
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CONFIG_HAVE_IFD_BIN=y
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CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
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CONFIG_PAYLOAD_LINUX=y
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CONFIG_PAYLOAD_FILE="site-local/transformers/linuxboot_bzImage"
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CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
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CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
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CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"
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@ -0,0 +1,15 @@
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if VENDOR_INVENTEC
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choice
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prompt "Mainboard model"
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source "src/mainboard/inventec/*/Kconfig.name"
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endchoice
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source "src/mainboard/inventec/*/Kconfig"
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config MAINBOARD_VENDOR
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default "Inventec"
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endif # VENDOR_INVENTEC
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@ -0,0 +1,2 @@
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config VENDOR_INVENTEC
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bool "Inventec"
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@ -0,0 +1,38 @@
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if BOARD_INVENTEC_TRANSFORMERS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_65536
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select CONSOLE_OVERRIDE_LOGLEVEL
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select IPMI_OCP
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select IPMI_KCS
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select IPMI_KCS_ROMSTAGE
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select MEMORY_MAPPED_TPM
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_USES_FSP2_0
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select SOC_INTEL_SAPPHIRERAPIDS_SP
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select SUPERIO_ASPEED_AST2400
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select HAVE_ACPI_TABLES
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select MAINBOARD_USES_IFD_GBE_REGION
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select VPD
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select OCP_VPD
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select OCP_EWL
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select SOC_INTEL_XEON_RAS
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select RUNTIME_CONFIGURABLE_SMM_LOGLEVEL
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config MAINBOARD_DIR
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default "inventec/transformers"
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config MAINBOARD_PART_NUMBER
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default "Transformers"
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
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config MAX_SOCKET
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default 2
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config DEBUG_SMI
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default y
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endif
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@ -0,0 +1,2 @@
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config BOARD_INVENTEC_TRANSFORMERS
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bool "Transformers"
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@ -0,0 +1,4 @@
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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@ -0,0 +1,37 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Enable ACPI _SWS methods */
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#include <soc/intel/common/acpi/acpi_wake_source.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (DBG0, SystemIO, 0x80, 0x02)
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Field (DBG0, ByteAcc, Lock, Preserve)
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{
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IO80, 8,
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IO81, 8
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}
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method (_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method (_WAK, 1)
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{
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Return (Package (){ 0, 0 })
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}
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@ -0,0 +1,13 @@
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FLASH 64M {
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SI_ALL@0x0 0x03000000 {
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SI_DESC@0x0 0x1000
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SI_GBE@0x1000 0x2000
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SI_ME@0x3000 0x2fed000
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SI_PT@0x2ff0000 0x10000
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}
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RW_MRC_CACHE@0x3000000 0x10000
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FMAP 0x800
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RW_VPD(PRESERVE) 0x4000
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RO_VPD(PRESERVE) 0x4000
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COREBOOT(CBFS)
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}
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@ -0,0 +1,6 @@
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Vendor name: Inventec
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Board name: Transformers
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Category: eval
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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@ -0,0 +1,39 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/intel/common/block/lpc/lpc_def.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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#define ASPEED_SIO_PORT 0x2E
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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void bootblock_mainboard_early_init(void)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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* For ArcherCity CRB, only SUART1 is used.
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*/
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uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
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uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
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/* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
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/* LPC I/O enable: com1 and com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
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/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
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pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
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pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
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const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
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aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
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}
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@ -0,0 +1,52 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/intel/xeon_sp/spr
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# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
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register "turbo_ratio_limit" = "0x181819191e242424"
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register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18"
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device domain 0 on
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 on end # Management Engine Interface 2
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device pci 16.6 on end # Management Engine IDE-R
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device pci 1f.0 on # Intel device 1b81: PCH eSPI controller
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chip superio/common
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device pnp 2e.0 on
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chip superio/aspeed/ast2400
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register "use_espi" = "1"
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device pnp 2e.2 on # SUART1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # SUART2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.4 off # System Wake-Up Control
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end
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device pnp 2e.5 off # Keyboard controller
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end
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device pnp 2e.7 off # GPIO
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end
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device pnp 2e.b off # Com3
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end
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device pnp 2e.c off # Com4
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end
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device pnp 2e.d off # LPC 2 AHB
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end
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device pnp 2e.e off # Mailbox
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end
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end
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end
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end
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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register "bmc_i2c_address" = "0x20"
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register "bmc_boot_timeout" = "60"
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register "wait_for_bmc" = "1"
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end
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device pnp 0c31.0 off
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end
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end
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end
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end
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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#include <acpi/dsdt_top.asl>
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// platform ACPI tables
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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// SPR-SP ACPI tables
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#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
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// LPC related entries
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Scope (\_SB.PC00)
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{
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#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
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}
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}
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_RAS_H
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#define MAINBOARD_RAS_H
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struct fru {
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const char *str;
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};
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struct fru *mainboard_ras_get_ch_map(void);
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#endif
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@ -0,0 +1,142 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _SPRSP_AC_IIO_H_
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#define _SPRSP_AC_IIO_H_
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#include <defs_iio.h>
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/* For now only set 3 fields and hard-coded others, should be extended in the future */
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#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \
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{ \
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.SLOTEIP = 0, \
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.SLOTHPCAP = 0, \
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.SLOTHPSUP = 0, \
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.SLOTPIP = 0, \
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.SLOTAIP = 0, \
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.SLOTMRLSP = 0, \
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.SLOTPCP = 0, \
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.SLOTABP = 0, \
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.SLOTIMP = slotimp, \
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.SLOTSPLS = 0, \
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.SLOTSPLV = 0, \
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.SLOTPSP = slotpsp, \
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.VppEnabled = 0, \
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.VppPort = 0, \
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.VppAddress = 0, \
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.MuxAddress = 0, \
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.ChannelID = 0, \
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.PciePortEnable = 1, \
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.PEXPHIDE = pexphide, \
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.HidePEXPMenu = 0, \
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.PciePortOwnership = 0, \
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.RetimerConnectCount = 0, \
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.PcieMaxPayload = 0x7, \
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.PciePortLinkSpeed = 0, \
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.DfxDnTxPresetGen3 = 0xFF \
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}
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/*
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* Standard ArcherCity IIO PCIe Port Table
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*/
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static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt0[] = {
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/* DMI port: array index 0 */
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CFG_UPD_PCIE_PORT(0, 0, 0),
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/* IOU0 (PE0): array index 1 ~ 8 */
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CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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/* IOU1 (PE1): array index 9 ~ 16 */
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CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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/* IOU2 (PE2): array index 17 ~ 24 */
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CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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/* IOU3 (PE3): array index 25 ~ 32 */
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CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(0, 1, 27), /* 48:03.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(0, 1, 29), /* 48:05.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(0, 1, 31), /* 48:07.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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/* IOU4 (PE4): array index 33 ~ 40 */
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CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(0, 1, 35), /* 59:03.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(0, 1, 37), /* 59:05.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(0, 1, 39), /* 59:07.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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/* ArcherCity doesn't use IOU5 ~ IOU6. */
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};
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static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt1[] = {
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/* DMI port: array index 0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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/* IOU0 (PE0): array index 1 ~ 8 */
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CFG_UPD_PCIE_PORT(0, 1, 1), /* 97:01.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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/* IOU1 (PE1): array index 9 ~ 16 */
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CFG_UPD_PCIE_PORT(0, 1, 9), /* a7:01.0 */
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
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CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU2 (PE2): array index 17 ~ 24 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 17), /* b7:01.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU3 (PE3): array index 25 ~ 32 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 25), /* c7:01.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 27), /* c7:03.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 29), /* c7:05.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 31), /* c7:07.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU4 (PE4): array index 33 ~ 40 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 33), /* d7:01.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 35), /* d7:03.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 37), /* d7:05.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 39), /* d7:07.0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* ArcherCity doesn't use IOU5 ~ IOU6. */
|
||||
};
|
||||
#endif /* _SPRSP_CL_IIO_H_ */
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef CFG_GPIO_H
|
||||
#define CFG_GPIO_H
|
||||
|
||||
#include <gpio.h>
|
||||
|
||||
/* Pad configuration was generated automatically using intelp2m utility */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
|
||||
/* ------- GPIO Community 0 ------- */
|
||||
|
||||
/* ------- GPIO Group GPPC_A ------- */
|
||||
_PAD_CFG_STRUCT(GPPC_A0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_A11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
PAD_CFG_GPO(GPPC_A12, 1, RSMRST),
|
||||
PAD_NC(GPPC_A13, NONE),
|
||||
PAD_NC(GPPC_A14, NONE),
|
||||
PAD_CFG_GPO(GPPC_A15, 0, RSMRST),
|
||||
_PAD_CFG_STRUCT(GPPC_A16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
|
||||
PAD_NC(GPPC_A17, NONE),
|
||||
PAD_CFG_GPO(GPPC_A18, 1, RSMRST),
|
||||
/* GPPC_A19 - RESERVED */
|
||||
|
||||
/* ------- GPIO Group GPPC_B ------- */
|
||||
_PAD_CFG_STRUCT(GPPC_B0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_B1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_B2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_B3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_B4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
PAD_NC(GPPC_B5, NONE),
|
||||
_PAD_CFG_STRUCT(GPPC_B6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_B7, NONE, RSMRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_B8, NONE, RSMRST, OFF, ACPI),
|
||||
_PAD_CFG_STRUCT(GPPC_B9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, RSMRST, OFF, ACPI),
|
||||
/* GPPC_B11 - n/a */
|
||||
PAD_NC(GPPC_B12, NONE),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_B13, NONE, RSMRST, OFF, ACPI),
|
||||
PAD_NC(GPPC_B14, NONE),
|
||||
PAD_NC(GPPC_B15, NONE),
|
||||
PAD_NC(GPPC_B16, NONE),
|
||||
PAD_NC(GPPC_B17, NONE),
|
||||
PAD_NC(GPPC_B18, NONE),
|
||||
PAD_NC(GPPC_B19, NONE),
|
||||
PAD_NC(GPPC_B20, NONE),
|
||||
PAD_NC(GPPC_B21, NONE),
|
||||
PAD_NC(GPPC_B22, NONE),
|
||||
_PAD_CFG_STRUCT(GPPC_B23, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
|
||||
/* ------- GPIO Group GPPC_S ------- */
|
||||
PAD_NC(GPPC_S0, NONE),
|
||||
_PAD_CFG_STRUCT(GPPC_S1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_NC(GPPC_S2, NONE),
|
||||
PAD_CFG_GPO(GPPC_S3, 1, RSMRST),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, RSMRST, OFF, ACPI),
|
||||
_PAD_CFG_STRUCT(GPPC_S5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_NC(GPPC_S6, NONE),
|
||||
_PAD_CFG_STRUCT(GPPC_S7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_S8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_S9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_S10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, RSMRST, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Community 1 ------- */
|
||||
|
||||
/* ------- GPIO Group GPPC_C ------- */
|
||||
/* GPPC_C0 - RESERVED */
|
||||
/* GPPC_C1 - RESERVED */
|
||||
_PAD_CFG_STRUCT(GPPC_C2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
|
||||
/* GPPC_C3 - RESERVED */
|
||||
/* GPPC_C4 - RESERVED */
|
||||
PAD_CFG_GPO(GPPC_C5, 0, DEEP),
|
||||
/* GPPC_C6 - RESERVED */
|
||||
/* GPPC_C7 - RESERVED */
|
||||
/* GPPC_C8 - RESERVED */
|
||||
/* GPPC_C9 - RESERVED */
|
||||
/* GPPC_C10 - RESERVED */
|
||||
/* GPPC_C11 - RESERVED */
|
||||
/* GPPC_C12 - RESERVED */
|
||||
/* GPPC_C13 - RESERVED */
|
||||
/* GPPC_C14 - RESERVED */
|
||||
/* GPPC_C15 - RESERVED */
|
||||
/* GPPC_C16 - RESERVED */
|
||||
PAD_CFG_GPO(GPPC_C17, 1, DEEP),
|
||||
PAD_CFG_GPO(GPPC_C18, 0, RSMRST),
|
||||
_PAD_CFG_STRUCT(GPPC_C19, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_C20, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
|
||||
PAD_CFG_GPO(GPPC_C21, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_NC(GPP_D3, UP_20K),
|
||||
PAD_NC(GPP_D4, UP_20K),
|
||||
PAD_NC(GPP_D5, UP_20K),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI),
|
||||
_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
PAD_NC(GPP_D9, UP_20K),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
/* GPP_D13 - RESERVED */
|
||||
_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
|
||||
_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Community 3 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_GPO(GPP_E0, 0, RSMRST),
|
||||
PAD_CFG_GPO(GPP_E1, 1, RSMRST),
|
||||
PAD_CFG_GPO(GPP_E2, 1, RSMRST),
|
||||
PAD_CFG_GPO(GPP_E3, 1, RSMRST),
|
||||
_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
PAD_CFG_GPO(GPP_E14, 0, RSMRST),
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
/* ------- GPIO Group JTAG ------- */
|
||||
|
||||
/* ------- GPIO Community 4 ------- */
|
||||
|
||||
/* ------- GPIO Group GPPC_H ------- */
|
||||
_PAD_CFG_STRUCT(GPPC_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
/* GPPC_H1 - RESERVED */
|
||||
PAD_NC(GPPC_H2, UP_20K),
|
||||
PAD_NC(GPPC_H3, UP_20K),
|
||||
PAD_NC(GPPC_H4, UP_20K),
|
||||
PAD_NC(GPPC_H5, UP_20K),
|
||||
_PAD_CFG_STRUCT(GPPC_H6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_NC(GPPC_H8, UP_20K),
|
||||
PAD_NC(GPPC_H9, NONE),
|
||||
PAD_NC(GPPC_H10, NONE),
|
||||
PAD_NC(GPPC_H11, NONE),
|
||||
PAD_NC(GPPC_H12, UP_20K),
|
||||
PAD_NC(GPPC_H13, UP_20K),
|
||||
PAD_NC(GPPC_H14, UP_20K),
|
||||
_PAD_CFG_STRUCT(GPPC_H15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_H16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPPC_H17, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_NC(GPPC_H18, NONE),
|
||||
_PAD_CFG_STRUCT(GPPC_H19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
_PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
|
||||
_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_J6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
|
||||
_PAD_CFG_STRUCT(GPP_J7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
|
||||
_PAD_CFG_STRUCT(GPP_J8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
||||
PAD_NC(GPP_J9, DN_20K),
|
||||
PAD_NC(GPP_J10, DN_20K),
|
||||
PAD_NC(GPP_J11, DN_20K),
|
||||
PAD_NC(GPP_J12, UP_1K),
|
||||
PAD_NC(GPP_J13, UP_1K),
|
||||
PAD_NC(GPP_J14, UP_1K),
|
||||
PAD_NC(GPP_J15, UP_1K),
|
||||
|
||||
/* ------- GPIO Community 5 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
PAD_NC(GPP_I0, UP_20K),
|
||||
PAD_NC(GPP_I1, UP_20K),
|
||||
PAD_NC(GPP_I2, UP_20K),
|
||||
PAD_NC(GPP_I3, UP_20K),
|
||||
PAD_NC(GPP_I4, UP_20K),
|
||||
PAD_NC(GPP_I5, UP_20K),
|
||||
PAD_NC(GPP_I6, UP_20K),
|
||||
PAD_NC(GPP_I7, UP_20K),
|
||||
PAD_NC(GPP_I8, UP_20K),
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 0, UP_20K, DEEP),
|
||||
PAD_NC(GPP_I10, UP_20K),
|
||||
PAD_CFG_TERM_GPO(GPP_I11, 0, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_I15, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
_PAD_CFG_STRUCT(GPP_I16, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
_PAD_CFG_STRUCT(GPP_I17, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
||||
PAD_CFG_TERM_GPO(GPP_I18, 0, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I19, 0, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I20, 0, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I21, 0, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, RSMRST, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPP_L ------- */
|
||||
_PAD_CFG_STRUCT(GPP_L0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
||||
/* GPP_L1 - RESERVED */
|
||||
_PAD_CFG_STRUCT(GPP_L2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
||||
PAD_NC(GPP_L3, NONE),
|
||||
PAD_NC(GPP_L4, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_L5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, PLTRST, OFF, DRIVER),
|
||||
PAD_NC(GPP_L7, NONE),
|
||||
PAD_NC(GPP_L8, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_M ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M4, DN_20K, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_NC(GPP_M9, DN_20K),
|
||||
PAD_NC(GPP_M10, DN_20K),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, RSMRST, OFF, ACPI),
|
||||
PAD_CFG_TERM_GPO(GPP_M12, 0, DN_20K, DEEP),
|
||||
PAD_NC(GPP_M13, DN_20K),
|
||||
PAD_NC(GPP_M14, DN_20K),
|
||||
PAD_NC(GPP_M15, UP_20K),
|
||||
PAD_NC(GPP_M16, UP_20K),
|
||||
PAD_NC(GPP_M17, UP_20K),
|
||||
|
||||
/* ------- GPIO Group GPP_N ------- */
|
||||
PAD_NC(GPP_N0, NONE),
|
||||
PAD_NC(GPP_N1, DN_20K),
|
||||
PAD_NC(GPP_N2, NONE),
|
||||
PAD_NC(GPP_N3, NONE),
|
||||
PAD_NC(GPP_N4, NONE),
|
||||
};
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <drivers/ipmi/ipmi_if.h>
|
||||
#include <drivers/ipmi/ipmi_ops.h>
|
||||
#include <drivers/ipmi/ocp/ipmi_ocp.h>
|
||||
#include <drivers/ocp/include/vpd.h>
|
||||
#include <drivers/vpd/vpd.h>
|
||||
#include <types.h>
|
||||
|
||||
#include "ipmi.h"
|
||||
|
||||
enum cb_err ipmi_get_slot_id(uint8_t *slot_id)
|
||||
{
|
||||
int ret;
|
||||
struct ipmi_config_rsp {
|
||||
struct ipmi_rsp resp;
|
||||
uint8_t board_sku_id;
|
||||
uint8_t board_rev_id;
|
||||
uint8_t slot_id;
|
||||
uint8_t slot_config_id;
|
||||
} __packed;
|
||||
struct ipmi_config_rsp rsp;
|
||||
|
||||
ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BOARD_ID, NULL, 0, (unsigned char *)&rsp, sizeof(rsp));
|
||||
|
||||
if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) {
|
||||
printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", __func__, ret, rsp.resp.completion_code);
|
||||
return CB_ERR;
|
||||
}
|
||||
*slot_id = rsp.slot_id;
|
||||
return CB_SUCCESS;
|
||||
}
|
||||
|
||||
void init_frb2_wdt(void)
|
||||
{
|
||||
uint8_t enable;
|
||||
int action, countdown;
|
||||
|
||||
if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) {
|
||||
printk(BIOS_DEBUG, "Got VPD %s value: %d\n", FRB2_TIMER, enable);
|
||||
} else {
|
||||
printk(BIOS_INFO, "Not able to get VPD %s, default set to %d\n", FRB2_TIMER,
|
||||
FRB2_TIMER_DEFAULT);
|
||||
enable = FRB2_TIMER_DEFAULT;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
if (vpd_get_int(FRB2_COUNTDOWN, VPD_RW_THEN_RO, &countdown)) {
|
||||
printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n",
|
||||
countdown * 100);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n",
|
||||
FRB2_COUNTDOWN_DEFAULT * 100);
|
||||
countdown = FRB2_COUNTDOWN_DEFAULT;
|
||||
}
|
||||
|
||||
if (vpd_get_int(FRB2_ACTION, VPD_RW_THEN_RO, &action)) {
|
||||
printk(BIOS_DEBUG, "FRB2 timer action set to: %d\n", action);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "FRB2 timer action use default value: %d\n",
|
||||
FRB2_ACTION_DEFAULT);
|
||||
action = FRB2_ACTION_DEFAULT;
|
||||
}
|
||||
ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, (uint16_t)countdown,
|
||||
(uint8_t)action);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Disable FRB2 timer\n");
|
||||
ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef TRANSFORMERS_IPMI_H
|
||||
#define TRANSFORMERS_IPMI_H
|
||||
|
||||
#include <types.h>
|
||||
|
||||
void init_frb2_wdt(void);
|
||||
enum cb_err ipmi_get_slot_id(uint8_t *slot_id);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <sprsp_gpio.h>
|
||||
#include <intelblocks/cse.h>
|
||||
#include <memory_info.h>
|
||||
|
||||
#include "ipmi.h"
|
||||
|
||||
#define SLOT_ID_LEN 2
|
||||
static char slot_id_str[SLOT_ID_LEN];
|
||||
extern uint32_t heci_fw_sts(void);
|
||||
extern uint32_t heci_cse_normal(void);
|
||||
extern uint32_t heci_cse_done(void);
|
||||
|
||||
//extern void cse_init(uintptr_t tempbar);
|
||||
|
||||
u8 smbios_mainboard_feature_flags(void)
|
||||
{
|
||||
return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
|
||||
}
|
||||
|
||||
const char *smbios_mainboard_location_in_chassis(void)
|
||||
{
|
||||
uint8_t slot_id = 0;
|
||||
if (ipmi_get_slot_id(&slot_id) != CB_SUCCESS) {
|
||||
printk(BIOS_ERR, "IPMI get slot_id failed\n");
|
||||
return "Part Component";
|
||||
}
|
||||
return slot_id_str;
|
||||
}
|
||||
|
||||
void mainboard_silicon_init_params(FSPS_UPD *params)
|
||||
{
|
||||
/* configure Emmitsburg PCH GPIO controller after FSP-M */
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <drivers/vpd/vpd.h>
|
||||
#include <drivers/ocp/include/vpd.h>
|
||||
#include <drivers/ipmi/ipmi_if.h>
|
||||
#include <drivers/ipmi/ocp/ipmi_ocp.h>
|
||||
#include <drivers/ocp/ewl/ocp_ewl.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <defs_cxl.h>
|
||||
#include <defs_iio.h>
|
||||
#include <sprsp_ac_iio.h>
|
||||
|
||||
#include "ipmi.h"
|
||||
|
||||
void mainboard_ewl_check(void)
|
||||
{
|
||||
/* Enhanced Warning Log prints EWL type 3 primarily associated with MRC training failures */
|
||||
get_ewl();
|
||||
}
|
||||
|
||||
static void mainboard_config_iio(FSPM_UPD *mupd)
|
||||
{
|
||||
int port;
|
||||
|
||||
UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
|
||||
(UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
|
||||
|
||||
/* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
|
||||
for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) {
|
||||
PciePortConfig[0].SLOTIMP[port] = ac_iio_pci_port_skt0[port].SLOTIMP;
|
||||
PciePortConfig[0].SLOTPSP[port] = ac_iio_pci_port_skt0[port].SLOTPSP;
|
||||
PciePortConfig[0].PciePortEnable[port] = ac_iio_pci_port_skt0[port].PciePortEnable;
|
||||
PciePortConfig[0].PEXPHIDE[port] = ac_iio_pci_port_skt0[port].PEXPHIDE;
|
||||
PciePortConfig[0].PcieMaxPayload[port] = ac_iio_pci_port_skt0[port].PcieMaxPayload;
|
||||
PciePortConfig[0].PciePortLinkSpeed[port] = ac_iio_pci_port_skt0[port].PciePortLinkSpeed;
|
||||
PciePortConfig[0].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt0[port].DfxDnTxPresetGen3;
|
||||
}
|
||||
/* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
|
||||
for (port = ARRAY_SIZE(ac_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
|
||||
PciePortConfig[0].PEXPHIDE[port] = 1;
|
||||
PciePortConfig[0].HidePEXPMenu[port] = 1;
|
||||
}
|
||||
PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16;
|
||||
PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16;
|
||||
PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16;
|
||||
PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_xxx8xxx8;
|
||||
PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_xxxxxx16;
|
||||
|
||||
PciePortConfig[0].PcieGlobalAspm = 0x1;
|
||||
PciePortConfig[0].PcieMaxReadRequestSize = 0x5;
|
||||
|
||||
/* Socket1: Array ac_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
|
||||
for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt1); port++) {
|
||||
PciePortConfig[1].SLOTIMP[port] = ac_iio_pci_port_skt1[port].SLOTIMP;
|
||||
PciePortConfig[1].SLOTPSP[port] = ac_iio_pci_port_skt1[port].SLOTPSP;
|
||||
PciePortConfig[1].PciePortEnable[port] = ac_iio_pci_port_skt1[port].PciePortEnable;
|
||||
PciePortConfig[1].PEXPHIDE[port] = ac_iio_pci_port_skt1[port].PEXPHIDE;
|
||||
PciePortConfig[1].PcieMaxPayload[port] = ac_iio_pci_port_skt1[port].PcieMaxPayload;
|
||||
PciePortConfig[1].PciePortLinkSpeed[port] = ac_iio_pci_port_skt1[port].PciePortLinkSpeed;
|
||||
PciePortConfig[1].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt1[port].DfxDnTxPresetGen3;
|
||||
}
|
||||
/* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
|
||||
for (port = ARRAY_SIZE(ac_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
|
||||
PciePortConfig[1].PEXPHIDE[port] = 1;
|
||||
PciePortConfig[1].HidePEXPMenu[port] = 1;
|
||||
}
|
||||
PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_x4x4x4x4;
|
||||
PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16;
|
||||
PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16;
|
||||
PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_xxxxxx16;
|
||||
PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_xxx8xxx8;
|
||||
|
||||
PciePortConfig[1].PcieGlobalAspm = 0x1;
|
||||
PciePortConfig[1].PcieMaxReadRequestSize = 0x5;
|
||||
|
||||
/* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */
|
||||
if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) {
|
||||
printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE);
|
||||
} else {
|
||||
/* Set socket 0 IIO PCIe PE1 to CXL mode */
|
||||
/* Set socket 1 IIO PCIe PE0 to CXL mode */
|
||||
/* eg. Protocl Auto Negotiation */
|
||||
mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL;
|
||||
mupd->FspmConfig.IioPcieSubSystemMode0[1] = IIO_MODE_CXL;
|
||||
|
||||
/* Disable CXL header bypass */
|
||||
mupd->FspmConfig.DfxCxlHeaderBypass = 0;
|
||||
|
||||
/* Set DFX CXL security level to fully trusted */
|
||||
mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED;
|
||||
|
||||
/* Set DelayAfterPCIeLinkTraining to 2000 ms */
|
||||
mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
uint8_t val;
|
||||
|
||||
/* Since it's the first IPMI command, it's better to run get BMC selftest result first */
|
||||
if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
|
||||
init_frb2_wdt();
|
||||
}
|
||||
|
||||
/* Send FSP log message to SOL */
|
||||
if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val))
|
||||
mupd->FspmConfig.SerialIoUartDebugEnable = val;
|
||||
else {
|
||||
printk(BIOS_INFO, "Not able to get VPD %s, default set "
|
||||
"SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT);
|
||||
mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT;
|
||||
}
|
||||
|
||||
/* Set Rank Margin Tool to disable. */
|
||||
mupd->FspmConfig.EnableRMT = 0x0;
|
||||
/* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on warm boots */
|
||||
/* Disable - Disables this feature */
|
||||
/*Auto - Sets it to the MRC default setting */
|
||||
mupd->FspmConfig.AttemptFastBoot = 0x1;
|
||||
/* Set Attempt Fast Cold Boot to enable */
|
||||
/* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on cold boots */
|
||||
/* Disable - Disables this feature */
|
||||
/* Auto - Sets it to the MRC default setting */
|
||||
mupd->FspmConfig.AttemptFastBootCold = 0x1;
|
||||
|
||||
/* Set Adv MemTest Option to 0. */
|
||||
mupd->FspmConfig.AdvMemTestOptions = 0x0;
|
||||
/* Set MRC Promote Warnings to disable. */
|
||||
/* Determines if MRC warnings are promoted to system level. */
|
||||
mupd->FspmConfig.promoteMrcWarnings = 0x0;
|
||||
/* Set Promote Warnings to disable. */
|
||||
/* Determines if warnings are promoted to system level. */
|
||||
mupd->FspmConfig.promoteWarnings = 0x0;
|
||||
|
||||
/* Reduce FSP debug message to Minimum */
|
||||
mupd->FspmConfig.serialDebugMsgLvl = 0x1;
|
||||
|
||||
/* Disable FSP memory train results */
|
||||
mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0;
|
||||
|
||||
mainboard_config_iio(mupd);
|
||||
}
|
||||
Loading…
Reference in New Issue