opencellular/rotundu: Introduce variants for OC
* Add Supabrck v1 variant * Modify rotundu base board Change-Id: Id20e9d4ed7ac071d25a69eee63c9ec544d2ad152 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Philipp Deppenwiese
Philipp Deppenwiese
parent
fa1f6ff09e
commit
d31d1f8bd1
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@ -15,10 +15,8 @@
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## GNU General Public License for more details.
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##
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if BOARD_OPENCELLULAR_ROTUNDU
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
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def_bool n
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select SOC_INTEL_FSP_BAYTRAIL
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_TABLES
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@ -30,13 +28,26 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select USE_BLOBS
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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config MAINBOARD_DIR
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if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
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config VARIANT_DIR
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string
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default "opencellular/rotundu"
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default "rotundu" if BOARD_OPENCELLULAR_ROTUNDU
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default "supabrckv1" if BOARD_OPENCELLULAR_SUPABRCKV1
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config MAINBOARD_PART_NUMBER
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string
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default "Rotundu"
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default "Rotundu" if BOARD_OPENCELLULAR_ROTUNDU
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default "Supabrck v1" if BOARD_OPENCELLULAR_SUPABRCKV1
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config DEVICETREE
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string
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default "variants/rotundu/devicetree.cb" if BOARD_OPENCELLULAR_ROTUNDU
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default "variants/supabrckv1/devicetree.cb" if BOARD_OPENCELLULAR_SUPABRCKV1
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config MAINBOARD_DIR
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string
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default "opencellular/rotundu"
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config MAINBOARD_VENDOR
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string
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@ -1,2 +1,7 @@
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config BOARD_OPENCELLULAR_ROTUNDU
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bool "Rotundu"
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bool "OpenCellular Rotundu (GBCv1)"
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select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
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config BOARD_OPENCELLULAR_SUPABRCKV1
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bool "OpenCellular Supabrck V1 (BRCK)"
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select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
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@ -13,5 +13,7 @@
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## GNU General Public License for more details.
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##
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ramstage-y += gpio.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-y += irqroute.c
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subdirs-y += variants/$(VARIANT_DIR)
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@ -17,7 +17,7 @@
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#include <stdlib.h>
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#include <soc/gpio.h>
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#include "irqroute.h"
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#include "../../irqroute.h"
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/* NCORE GPIOs */
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static const struct soc_gpio_map gpncore_gpio_map[] = {
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@ -0,0 +1,81 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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## Copyright (C) 2017-present Facebook, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/fsp_baytrail
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#### ACPI Register Settings ####
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register "fadt_pm_profile" = "PM_UNSPECIFIED"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
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#### FSP register settings ####
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register "PcdSataMode" = "SATA_MODE_AHCI"
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register "PcdMrcInitSPDAddr1" = "0xa0"
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register "PcdMrcInitSPDAddr2" = "0xa2"
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register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
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register "PcdeMMCBootMode" = "EMMC_DISABLED"
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register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
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register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
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register "PcdGttSize" = "GTT_SIZE_DEFAULT"
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register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
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register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
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register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
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register "EnableMemoryDown" = "MEMORY_DOWN_DISABLE"
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register "DIMM0Enable" = "DIMM0_ENABLE"
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register "DIMM1Enable" = "DIMM1_DISABLE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # 8086 0F00 - SoC router
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device pci 02.0 on end # 8086 0F31 - GFX
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device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
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device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
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device pci 11.0 off end # 8086 0F15 - SDIO Port (SD2 pins)
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device pci 12.0 off end # 8086 0F16 - SD Port (SD3 pins)
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device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
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device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
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device pci 15.0 off end # 8086 0F28 - LP Engine Audio
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device pci 16.0 off end # 8086 0F37 - OTG controller
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device pci 17.0 off end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
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device pci 18.0 on end # 8086 0F40 - SIO - DMA
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device pci 18.1 on end # 8086 0F41 - I2C Port 1
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device pci 18.2 off end # 8086 0F42 - I2C Port 2
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device pci 18.3 on end # 8086 0F43 - I2C Port 3
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device pci 18.4 off end # 8086 0F44 - I2C Port 4
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device pci 18.5 off end # 8086 0F45 - I2C Port 5
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device pci 18.6 off end # 8086 0F46 - I2C Port 6
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device pci 18.7 off end # 8086 0F47 - I2C Port 7
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device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
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device pci 1b.0 off end # 8086 0F04 - HD Audio
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device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (RADIO CARD)
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device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (GBE PHY 1)
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device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (GBE PHY 2)
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device pci 1c.3 off end # 8086 0F4E - PCIe Root Port 4 (NC)
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device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
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device pci 1e.0 on end # 8086 0F06 - SIO - DMA
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device pci 1e.1 off end # 8086 0F08 - PWM 1
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device pci 1e.2 off end # 8086 0F09 - PWM 2
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device pci 1e.3 on end # 8086 0F0A - HSUART 1
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device pci 1e.4 off end # 8086 0F0C - HSUART 2
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device pci 1e.5 off end # 8086 0F0E - SPI
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device pci 1f.0 on end # 8086 0F1C - LPC bridge
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device pci 1f.3 on end # 8086 0F12 - SMBus 0
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end
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end
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@ -0,0 +1,362 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2017-present Facebook, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdlib.h>
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#include <soc/gpio.h>
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#include "../../irqroute.h"
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/* NCORE GPIOs */
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static const struct soc_gpio_map gpncore_gpio_map[] = {
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GPIO_FUNC2, /* GPIO 0 */
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GPIO_FUNC2, /* GPIO 1 */
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GPIO_FUNC2, /* GPIO 2 */
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GPIO_FUNC2, /* GPIO 3 */
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GPIO_FUNC2, /* GPIO 4 */
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GPIO_FUNC2, /* GPIO 5 */
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GPIO_FUNC2, /* GPIO 6 */
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GPIO_FUNC2, /* GPIO 7 */
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GPIO_FUNC2, /* GPIO 8 */
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GPIO_FUNC2, /* GPIO 9 */
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GPIO_FUNC2, /* GPIO 10 */
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GPIO_FUNC2, /* GPIO 11 */
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GPIO_FUNC2, /* GPIO 12 */
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GPIO_FUNC2, /* GPIO 13 */
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GPIO_FUNC2, /* GPIO 14 */
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GPIO_FUNC2, /* GPIO 15 */
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GPIO_FUNC2, /* GPIO 16 */
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GPIO_FUNC2, /* GPIO 17 */
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GPIO_FUNC2, /* GPIO 18 */
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GPIO_FUNC2, /* GPIO 19 */
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GPIO_FUNC2, /* GPIO 20 */
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GPIO_FUNC2, /* GPIO 21 */
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GPIO_FUNC2, /* GPIO 22 */
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GPIO_FUNC2, /* GPIO 23 */
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GPIO_FUNC2, /* GPIO 24 */
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GPIO_FUNC2, /* GPIO 25 */
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GPIO_FUNC2, /* GPIO 26 */
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GPIO_END};
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/* SCORE GPIOs (GPIO_S0_SC_XX) */
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static const struct soc_gpio_map gpscore_gpio_map[] = {
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GPIO_NC,
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/* GPIO_S0_SC[000] SATA_GP[0] */
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GPIO_NC,
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/* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/
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GPIO_FUNC1,
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/* GPIO_S0_SC[002] SATA_LED# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */
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GPIO_FUNC2,
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/* GPIO_S0_SC[007] RESERVED SD3_WP */
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GPIO_NC,
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/* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/
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GPIO_NC,
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/* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/
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GPIO_NC,
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/* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */
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GPIO_NC,
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/* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */
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GPIO_NC,
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/* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/
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GPIO_NC,
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/* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/
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GPIO_NC,
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/* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/
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GPIO_DEFAULT,
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/* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/
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GPIO_NC,
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/* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
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GPIO_NC,
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/* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
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GPIO_NC,
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/* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
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GPIO_NC,
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/* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
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GPIO_NC,
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/* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
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GPIO_NC,
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/* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
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GPIO_NC,
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/* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
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GPIO_NC,
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/* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
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GPIO_NC,
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/* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
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GPIO_NC,
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/* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
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GPIO_NC,
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/* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
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GPIO_NC,
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/* GPIO_S0_SC[027] SD2_CLK */
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GPIO_NC,
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/* GPIO_S0_SC[028] SD2_D[0] */
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GPIO_NC,
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/* GPIO_S0_SC[029] SD2_D[1] */
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GPIO_NC,
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/* GPIO_S0_SC[030] SD2_D[2] */
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GPIO_NC,
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/* GPIO_S0_SC[031] SD2_D[3]_CD# */
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GPIO_NC,
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/* GPIO_S0_SC[032] SD2_CMD */
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GPIO_NC,
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/* GPIO_S0_SC[033] SD3_CLK */
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GPIO_NC,
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/* GPIO_S0_SC[034] SD3_D[0] */
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GPIO_NC,
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/* GPIO_S0_SC[035] SD3_D[1] */
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GPIO_NC,
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/* GPIO_S0_SC[036] SD3_D[2] */
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GPIO_NC,
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/* GPIO_S0_SC[037] SD3_D[3] */
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GPIO_NC,
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/* GPIO_S0_SC[038] SD3_CD# */
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GPIO_NC,
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/* GPIO_S0_SC[039] SD3_CMD */
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GPIO_FUNC1,
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/* GPIO_S0_SC[040] SD3_1P8EN */
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GPIO_FUNC1,
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/* GPIO_S0_SC[041] SD3_PWREN# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[042] ILB_LPC_AD[0] */
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GPIO_FUNC1,
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/* GPIO_S0_SC[043] ILB_LPC_AD[1] */
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GPIO_FUNC1,
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/* GPIO_S0_SC[044] ILB_LPC_AD[2] */
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GPIO_FUNC1,
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/* GPIO_S0_SC[045] ILB_LPC_AD[3] */
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GPIO_FUNC1,
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/* GPIO_S0_SC[046] ILB_LPC_FRAME# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[047] ILB_LPC_CLK[0] */
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GPIO_NC,
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/* GPIO_S0_SC[048] ILB_LPC_CLK[1] */
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GPIO_FUNC1,
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/* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[050] ILB_LPC_SERIRQ */
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GPIO_FUNC1,
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/* GPIO_S0_SC[051] PCU_SMB_DATA */
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GPIO_FUNC1,
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/* GPIO_S0_SC[052] PCU_SMB_CLK */
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GPIO_FUNC1,
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/* GPIO_S0_SC[053] PCU_SMB_ALERT# */
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GPIO_NC,
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/* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/
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GPIO_DEFAULT,
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/* GPIO_S0_SC[055] RESERVED */
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GPIO_DEFAULT,
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/* GPIO_S0_SC[056] RESERVED */
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GPIO_FUNC1,
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/* GPIO_S0_SC[057] PCU_UART_TXD */
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GPIO_DEFAULT,
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/* GPIO_S0_SC[058] RESERVED */
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GPIO_DEFAULT,
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/* GPIO_S0_SC[059] RESERVED */
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GPIO_DEFAULT,
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/* GPIO_S0_SC[060] RESERVED */
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GPIO_FUNC1,
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/* GPIO_S0_SC[061] PCU_UART_RXD */
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GPIO_NC,
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/* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */
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GPIO_FUNC1,
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/* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/
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GPIO_NC,
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/* GPIO_S0_SC[064] LPE_I2S2_DATAIN */
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GPIO_FUNC1,
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/* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/
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GPIO_NC,
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/* GPIO_S0_SC[066] SIO_SPI_CS# */
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GPIO_NC,
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/* GPIO_S0_SC[067] SIO_SPI_MISO */
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GPIO_NC,
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/* GPIO_S0_SC[068] SIO_SPI_MOSI */
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GPIO_NC,
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/* GPIO_S0_SC[069] SIO_SPI_CLK */
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GPIO_FUNC1,
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/* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/
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GPIO_FUNC1,
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/* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/
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GPIO_NC,
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/* GPIO_S0_SC[072] SIO_UART1_RTS# */
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GPIO_DEFAULT,
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/* GPIO_S0_SC[073] SIO_UART1_CTS# */
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GPIO_NC,
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/* GPIO_S0_SC[074] SIO_UART2_RXD */
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GPIO_NC,
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/* GPIO_S0_SC[075] SIO_UART2_TXD */
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GPIO_NC,
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/* GPIO_S0_SC[076] SIO_UART2_RTS# */
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GPIO_NC,
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/* GPIO_S0_SC[077] SIO_UART2_CTS# */
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GPIO_FUNC1,
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/* GPIO_S0_SC[078] SIO_I2C0_DATA */
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GPIO_FUNC1,
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/* GPIO_S0_SC[079] SIO_I2C0_CLK */
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GPIO_NC,
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/* GPIO_S0_SC[080] SIO_I2C1_DATA */
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GPIO_NC,
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/* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/
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GPIO_FUNC1,
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/* GPIO_S0_SC[082] SIO_I2C2_DATA */
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GPIO_FUNC1,
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/* GPIO_S0_SC[083] SIO_I2C2_CLK */
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GPIO_NC,
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/* GPIO_S0_SC[084] SIO_I2C3_DATA */
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GPIO_NC,
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/* GPIO_S0_SC[085] SIO_I2C3_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[086] SIO_I2C4_DATA */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[087] SIO_I2C4_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[088] SIO_I2C5_DATA */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[089] SIO_I2C5_CLK */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */
|
||||
GPIO_NC,
|
||||
/* RESERVED GPIO_S0_SC[092] */
|
||||
GPIO_NC,
|
||||
/* RESERVED GPIO_S0_SC[093] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[094] SIO_PWM[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[095] SIO_PWM[1] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[096] PMC_PLT_CLK[0] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[097] PMC_PLT_CLK[1] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[098] PMC_PLT_CLK[2] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[099] PMC_PLT_CLK[3] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[100] PMC_PLT_CLK[4] */
|
||||
GPIO_NC,
|
||||
/* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/
|
||||
GPIO_END};
|
||||
|
||||
/* SSUS GPIOs (GPIO_S5) */
|
||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[00] RESERVED- */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[10] RESERVED RESERVED RESERVED*/
|
||||
GPIO_DEFAULT,
|
||||
/* PMC_SUSPWRDNACK GPIO_S5[11]*/
|
||||
GPIO_NC,
|
||||
/* PMC_SUSCLK[0] GPIO_S5[12]*/
|
||||
GPIO_NC,
|
||||
/* RESERVED GPIO_S5[13]*/
|
||||
GPIO_FUNC2,
|
||||
/* RESERVED GPIO_S5[14] USB_ULPI_RST#*/
|
||||
GPIO_FUNC0,
|
||||
/* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/
|
||||
GPIO_FUNC0,
|
||||
/* PMC_PWRBTN# GPIO_S5[16]*/
|
||||
GPIO_FUNC1,
|
||||
/* RESERVED GPIO_S5[17]*/
|
||||
GPIO_FUNC0,
|
||||
/* PMC_SUS_STAT# GPIO_S5[18]*/
|
||||
GPIO_FUNC0,
|
||||
/* USB_OC[0]# GPIO_S5[19]*/
|
||||
GPIO_FUNC0,
|
||||
/* USB_OC[1]# GPIO_S5[20]*/
|
||||
GPIO_NC,
|
||||
/* PCU_SPI_CS[1]# GPIO_S5[21]*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_DEFAULT,
|
||||
/* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
|
||||
GPIO_FUNC1,
|
||||
/* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/
|
||||
GPIO_NC,
|
||||
/* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/
|
||||
GPIO_END};
|
||||
|
||||
static struct soc_gpio_config gpio_config = {
|
||||
.ncore = gpncore_gpio_map,
|
||||
.score = gpscore_gpio_map,
|
||||
.ssus = gpssus_gpio_map,
|
||||
.core_dirq = NULL,
|
||||
.sus_dirq = NULL,
|
||||
};
|
||||
|
||||
struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; }
|
||||
Loading…
Reference in New Issue