diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 1c37cc3616..30e7e592bc 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -28,7 +28,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SMP
 	select SSE2
 	select UDELAY_LAPIC
-	select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
+	select SUPPORT_CPU_UCODE_IN_CBFS
 	select PARALLEL_CPU_INIT
 	select TSC_SYNC_MFENCE
 	select LAPIC_MONOTONIC_TIMER
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index b25c9979e9..5482e74b7a 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -22,6 +22,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 #include "model_406dx.h"
@@ -168,6 +169,9 @@ static void model_406dx_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
+	/* Load microcode */
+	intel_update_microcode_from_cbfs();
+
 	/* Clear out pending MCEs */
 	configure_mca();