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amd/mtrr: Fix IORR MTRR 

IORR MTRR definitions renamed to avoid collision
between <cpu/amd/mtrr.h> and <AGESA.h>.

Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29352
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2018-10-30 07:07:00 +01:00 committed by Patrick Georgi
parent c4ba0f4cbd
commit d35c7fe1bf
4 changed files with 11 additions and 21 deletions
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2
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -138,7 +138,7 @@ void amd_setup_mtrrs(void)
* undefined side effects. * undefined side effects.
*/ */
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
for (i = IORR_FIRST; i <= IORR_LAST; i++) for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++)
wrmsr(i, msr); wrmsr(i, msr);
/* Enable Variable Mtrrs /* Enable Variable Mtrrs

18
src/include/cpu/amd/mtrr.h
View File

@ -1,20 +1,10 @@
#ifndef CPU_AMD_MTRR_H #ifndef CPU_AMD_MTRR_H
#define CPU_AMD_MTRR_H #define CPU_AMD_MTRR_H
/* FIXME #define MTRR_IORR0_BASE 0xC0010016
* Replace #define MTRR_IORR0_MASK 0xC0010017
* #define IORR_FIRST 0xC0010016 #define MTRR_IORR1_BASE 0xC0010018
* #define IORR_LAST 0xC0010019 #define MTRR_IORR1_MASK 0xC0010019
* with
* #define IORR0_BASE 0xC0010016
* #define IORR0_MASK 0xC0010017
* #define IORR1_BASE 0xC0010018
* #define IORR1_MASK 0xC0010019
* those are also defined in vendorcode <AGESA.h> file.
*/
#define IORR_FIRST 0xC0010016
#define IORR_LAST 0xC0010019
#define MTRR_READ_MEM (1 << 4) #define MTRR_READ_MEM (1 << 4)
#define MTRR_WRITE_MEM (1 << 3) #define MTRR_WRITE_MEM (1 << 3)

6
src/northbridge/amd/amdmct/mct/mctdqs_d.c
View File

@ -816,10 +816,10 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi; u32 lo, hi;
hi = TestAddr >> 24; hi = TestAddr >> 24;
lo = TestAddr << 8; lo = TestAddr << 8;
_WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */ _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF; hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */ lo = 0xFC000800; /* 64MB Mask */
_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
} }
@ -829,7 +829,7 @@ void ResetTargetWTIO_D(void)
hi = 0; hi = 0;
lo = 0; lo = 0;
_WRMSR(0xc0010017, lo, hi); // IORR0 Mask _WRMSR(MTRR_IORR0_MASK, lo, hi); // IORR0 Mask
} }

6
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
View File

@ -2148,10 +2148,10 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi; u32 lo, hi;
hi = TestAddr >> 24; hi = TestAddr >> 24;
lo = TestAddr << 8; lo = TestAddr << 8;
_WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */ _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF; hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */ lo = 0xFC000800; /* 64MB Mask */
_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
} }
void ResetTargetWTIO_D(void) void ResetTargetWTIO_D(void)
@ -2160,7 +2160,7 @@ void ResetTargetWTIO_D(void)
hi = 0; hi = 0;
lo = 0; lo = 0;
_WRMSR(0xc0010017, lo, hi); /* IORR0 Mask */ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
} }
u32 SetUpperFSbase(u32 addr_hi) u32 SetUpperFSbase(u32 addr_hi)