diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index ed44f4fec1..6ecb689790 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -38,6 +38,8 @@ chip soc/intel/cannonlake
 	register "PchPmSlpSusMinAssert" = "4" # 4s
 	register "PchPmSlpAMinAssert" = "4"   # 2s
 	register "PchUnlockGpioPads" = "1"
+	# USB2 PHY Power gating
+	register "PchUsb2PhySusPgDisable" = "1"
 
 	register "speed_shift_enable" = "1"
 	register "psys_pmax" = "140"
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 4af8ca25ca..6bc3df11af 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -27,6 +27,8 @@ chip soc/intel/cannonlake
 	register "PchPmSlpSusMinAssert" = "4" # 4s
 	register "PchPmSlpAMinAssert" = "4"   # 2s
 	register "PchUnlockGpioPads" = "1"
+	# USB2 PHY Power gating
+	register "PchUsb2PhySusPgDisable" = "1"
 
 	register "speed_shift_enable" = "1"
 	register "psys_pmax" = "140"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index cd216e593b..b2aa8d5e8d 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -30,6 +30,8 @@ chip soc/intel/cannonlake
 	register "PchPmSlpS4MinAssert" = "4"  # 4s
 	register "PchPmSlpSusMinAssert" = "4" # 4s
 	register "PchPmSlpAMinAssert" = "4"   # 2s
+	# USB2 PHY Power gating
+	register "PchUsb2PhySusPgDisable" = "1"
 
 	register "speed_shift_enable" = "1"
 	register "s0ix_enable" = "1"
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 507290f504..f08fd0a95e 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -130,6 +130,8 @@ struct soc_intel_cannonlake_config {
 	uint16_t usb2_wake_enable_bitmap;
 	/* Wake Enable Bitmap for USB3 ports */
 	uint16_t usb3_wake_enable_bitmap;
+	/* USB2 PHY power gating */
+	uint8_t PchUsb2PhySusPgDisable;
 
 	/* SATA related */
 	enum {
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0713ef4604..dfc7e22522 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -273,6 +273,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 	}
 
+	if (config->PchUsb2PhySusPgDisable)
+		params->PchUsb2PhySusPgEnable = 0;
+
 	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;