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mb/google/brya/var/kinox: Enable PCIe WLAN 

Enable PCIe WLAN for Kinox
1. Enable PCI port 5 for PCIe WLAN
2. Enable CLKREQ, CLK SRC 2 for PCI port 5

BUG=b:236175551
TEST=Build and boot to OS in Kinox. Ensure that the WLAN module is
enumerated in the output of lspci.
localhost ~ # lspci
02:00.0 Network controller: Realtek Semiconductor Co., Ltd.Device
c852 (rev 01)

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3fbeadc85c9c88f5d178326dbbc83762083fe59a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65168
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
This commit is contained in:
Ian Feng 2022-06-16 15:17:06 +08:00 committed by Felix Held
parent 27d6299d51
commit d36aca5e22
2 changed files with 23 additions and 0 deletions
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2
src/mainboard/google/brya/variants/kinox/gpio.c
View File

@ -70,6 +70,8 @@ static const struct pad_config override_gpio_table[] = {
/* F16 : GSXCLK ==> NC */ /* F16 : GSXCLK ==> NC */
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
/* H12 : I2C7_SDA ==> NC */ /* H12 : I2C7_SDA ==> NC */
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
/* H23 : SRCCLKREQ5# ==> NC */ /* H23 : SRCCLKREQ5# ==> NC */

21
src/mainboard/google/brya/variants/kinox/overridetree.cb
View File

@ -7,6 +7,9 @@ fw_config
end end
chip soc/intel/alderlake chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_H"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |
@ -195,6 +198,24 @@ chip soc/intel/alderlake
device generic 0 alias dptf_policy on end device generic 0 alias dptf_policy on end
end end
end end
device ref pcie_rp5 on
# Enable WLAN PCIE 5 using clk 2
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
device pci 00.0 on end
end
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end
device ref pcie_rp6 on device ref pcie_rp6 on
# Enable PCIe-to-eMMC bridge PCIE 6 using clk 1 # Enable PCIe-to-eMMC bridge PCIE 6 using clk 1
register "pch_pcie_rp[PCH_RP(6)]" = "{ register "pch_pcie_rp[PCH_RP(6)]" = "{