mb/google/{poppy,nautilus,soraka}: Disable deep S3
Poppy and variants won't be using deep S3. This change disables deep S3 option in devicetree. BUG=b:69053636 Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22378 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -2,7 +2,7 @@ chip soc/intel/skylake
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# Deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "1"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
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@ -2,7 +2,7 @@ chip soc/intel/skylake
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# Deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "1"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
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@ -2,7 +2,7 @@ chip soc/intel/skylake
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# Deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "1"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
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