mb/pcengines: Remove unneeded includes and dead code
Fix coding style. Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS
Felix Held
parent
df946b8696
commit
d37a5bc29e
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@ -1,6 +1,6 @@
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chip northbridge/amd/lx
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device domain 0 on
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device pci 1.0 on end
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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@ -25,7 +25,7 @@ chip northbridge/amd/lx
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci f.0 on # ISA Bridge
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device pci f.0 on # ISA Bridge
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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@ -14,9 +14,6 @@
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*/
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include "southbridge/amd/cs5536/cs5536.h"
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/* Platform IRQs */
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#define PIRQA 11
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@ -53,15 +50,15 @@
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*
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* The only devices that interrupt are:
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*
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* What Device IRQ PIN PIN WIRED TO
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* What Device IRQ PIN PIN WIRED TO
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* -------------------------------------------------
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* AES 00:01.2 0a 01 A A
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* 3VPCI 00:0c.0 0a 01 A A
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* eth0 00:0d.0 0b 01 A B
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* mpci 00:0e.0 0a 01 A A
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* usb 00:0f.3 0b 02 B B
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* usb 00:0f.4 0b 04 D D
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* usb 00:0f.5 0b 04 D D
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* AES 00:01.2 0a 01 A A
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* 3VPCI 00:0c.0 0a 01 A A
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* eth0 00:0d.0 0b 01 A B
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* mpci 00:0e.0 0a 01 A A
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* usb 00:0f.3 0b 02 B B
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* usb 00:0f.4 0b 04 D D
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* usb 00:0f.5 0b 04 D D
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*
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* The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
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*/
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@ -71,7 +68,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_VERSION,
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */
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Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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} /* End Scope GPE */
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/* Contains the GPEs for USB overcurrent */
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#include "usb_oc.asl"
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@ -49,7 +49,7 @@ Method(\_PTS, 1) {
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/* On older chips, clear PciExpWakeDisEn */
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/*if (LLessEqual(\_SB.SBRI, 0x13)) {
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* Store(0,\_SB.PWDE)
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* Store(0,\_SB.PWDE)
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*}
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*/
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@ -64,4 +64,4 @@ Scope(\_GPE) { /* Start Scope GPE */
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Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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} /* End Scope GPE */
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@ -46,7 +46,7 @@ DefinitionBlock (
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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@ -14,54 +14,11 @@
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <string.h>
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#include <stdint.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#if 0
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u8 picr_data[FCH_INT_TABLE_SIZE] = {
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0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
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0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */
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0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
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0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
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0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
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// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
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0x00,0x00,0x1F /* 60 - 62 */
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};
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u8 intr_data[FCH_INT_TABLE_SIZE] = {
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0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
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0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
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0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */
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0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
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0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
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0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
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0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
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// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
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0x00,0x00,0x1F /* 60 - 62 */
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};
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#endif
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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