Add the Wyse S50 thin client to Coreboot.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Stefan Reinauer
parent
133887d540
commit
d37ce2e28e
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@ -100,6 +100,8 @@ config VENDOR_VIA
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bool "VIA"
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config VENDOR_WINENT
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bool "Win Enterprises"
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config VENDOR_WYSE
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bool "Wyse"
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endchoice
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@ -373,6 +375,16 @@ config MAINBOARD_VENDOR
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default "Win Enterprise"
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depends on VENDOR_WINENT
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config MAINBOARD_VENDOR
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string
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default "Wyse"
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depends on VENDOR_WYSE
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x102d
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depends on VENDOR_WYSE
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source "src/mainboard/a-trend/Kconfig"
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source "src/mainboard/abit/Kconfig"
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source "src/mainboard/advantech/Kconfig"
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@ -421,6 +433,7 @@ source "src/mainboard/thomson/Kconfig"
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source "src/mainboard/tyan/Kconfig"
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source "src/mainboard/via/Kconfig"
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source "src/mainboard/winent/Kconfig"
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source "src/mainboard/wyse/Kconfig"
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config BOARD_ROMSIZE_KB_128
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bool
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@ -0,0 +1,8 @@
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choice
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prompt "Mainboard model"
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depends on VENDOR_WYSE
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source "src/mainboard/wyse/s50/Kconfig"
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endchoice
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@ -0,0 +1,51 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config BOARD_WYSE_S50
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bool "S50"
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select ARCH_X86
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select CPU_AMD_GX2
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select NORTHBRIDGE_AMD_GX2
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select SOUTHBRIDGE_AMD_CS5536
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select ROMCC
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select UDELAY_TSC
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select BOARD_ROMSIZE_KB_256
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config MAINBOARD_DIR
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string
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default wyse/s50
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depends on BOARD_WYSE_S50
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config MAINBOARD_PART_NUMBER
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string
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default "s50"
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depends on BOARD_WYSE_S50
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config HAVE_OPTION_TABLE
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bool
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default n
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depends on BOARD_WYSE_S50
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config IRQ_SLOT_COUNT
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int
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default 3
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depends on BOARD_WYSE_S50
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@ -0,0 +1,5 @@
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {
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int nicirq;
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};
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@ -0,0 +1,74 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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@ -0,0 +1,32 @@
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chip northbridge/amd/gx2
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register "irqmap" = "0xaa5b"
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register "setupflash" = "0"
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device lapic_cluster 0 on
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chip cpu/amd/model_gx2
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "1"
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register "com1_address" = "0x3F8"
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register "com1_irq" = "4"
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register "com2_enable" = "0"
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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device pci e.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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end
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@ -0,0 +1,49 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 200x TODO <TODO@TODO>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
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0x00, /* Interrupt router bus */
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(0x0f << 3) | 0x0, /* Interrupt router dev */
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0, /* IRQs devoted exclusively to PCI usage */
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0x100b, /* Vendor */
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0x2b, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xdc, /* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum).
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*/
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x0f << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x5, 0x0},
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{0x00, (0x0d << 3) | 0x0, {{0x04, 0x0400}, {0x03, 0x0400}, {0x02, 0x0020}, {0x01, 0x0800}}, 0x1, 0x0},
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{0x00, (0x0e << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x2, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,12 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("WYSE S50 Mainboard")
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};
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@ -0,0 +1,167 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include <console/console.h>
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#include "lib/ramtest.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/gx2/raminit.h"
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static inline unsigned int ctz(unsigned int n)
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{
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int zeros;
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n = (n ^ (n - 1)) >> 1;
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for (zeros = 0; n; zeros++)
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{
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n >>= 1;
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}
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return zeros;
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5) */
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/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
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msr_t msr;
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unsigned char module_banks, val;
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uint16_t dimm_size;
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msr = rdmsr(MC_CF07_DATA);
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/* get module banks (sides) per dimm, SPD byte 5 */
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module_banks = spd_read_byte(0xA0, 5);
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if (module_banks < 1 || module_banks > 2)
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print_err("Module banks per dimm\n");
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module_banks >>= 1;
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msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
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msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
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/* get component banks per module bank, SPD byte 17 */
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val = spd_read_byte(0xA0, 17);
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if (val < 2 || val > 4)
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print_err("Component banks per module bank\n");
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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dimm_size = spd_read_byte(0xA0, 31);
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dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
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dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
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/* Module Density * Module Banks */
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dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
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if (dimm_size != 0) {
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dimm_size = ctz(dimm_size);
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}
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if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
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print_err("Only support up to 512MB \n");
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hlt();
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}
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msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
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/* page size = 2^col address */
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val = spd_read_byte(0xA0, 4);
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val -= 7;
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msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
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print_debug("computed msr.hi ");
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print_debug_hex32(msr.hi);
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print_debug("\n");
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msr.lo = 0x00003400;
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wrmsr(MC_CF07_DATA, msr);
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msr = rdmsr(MC_CF8F_DATA);
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msr.hi = 0x18000008;
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msr.lo = 0x296332a3;
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wrmsr(MC_CF8F_DATA, msr);
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}
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#include "northbridge/amd/gx2/raminit.c"
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#include "lib/generic_sdram.c"
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#include "northbridge/amd/gx2/pll_reset.c"
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#include "cpu/amd/model_gx2/cpureginit.c"
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#include "cpu/amd/model_gx2/syspreinit.c"
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static void msr_init(void)
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{
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/* total physical memory */
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__builtin_wrmsr(0x1808, 0x11f6bf00, 0x21c00002);
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/* traditional memory 0kB-512kB, 512kB-1MB */
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2dfbc040);
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__builtin_wrmsr(0x10000028, 0x6bf00100, 0x2000001f);
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__builtin_wrmsr(0x1000002c, 0xffff0003, 0x2000ffff);
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__builtin_wrmsr(0x10000080, 0x3, 0x0);
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__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
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__builtin_wrmsr(0x40000029, 0x6bf00100, 0x2000001f);
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__builtin_wrmsr(0x4000002d, 0xffff0003, 0x2000ffff);
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__builtin_wrmsr(0x40000080, 0x1, 0x0);
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__builtin_wrmsr(0x50002001, 0x27, 0x0);
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__builtin_wrmsr(0x4c002001, 0x1, 0x0);
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/* put code in northbridge[init].c here */
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}
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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};
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SystemPreInit();
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msr_init();
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cs5536_early_setup();
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/* disable the power button */
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outl(0x00, PMS_IO_BASE + 0x40);
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cs5536_setup_onchipuart(1);
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uart_init();
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console_init();
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pll_reset();
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cpuRegInit();
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print_err("done cpuRegInit\n");
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sdram_initialize(1, memctrl);
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print_err("ram setup done\n");
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/* Check all of memory */
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/*ram_check(0x00000000, 640*1024);*/
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print_err("ram check done\n");
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}
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