Add support for SMSC MEC1308/1310 SuperI/O EC
Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
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6626d6a9e3
commit
d3801f4f6f
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@ -40,6 +40,8 @@ config SUPERIO_SMSC_SIO1007
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bool
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config SUPERIO_SMSC_KBC1100
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bool
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config SUPERIO_SMSC_MEC1308
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bool
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config SUPERIO_SMSC_SMSCSUPERIO
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bool
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config SUPERIO_SMSC_SIO1036
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@ -29,6 +29,7 @@ subdirs-y += lpc47n227
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subdirs-y += sio10n268
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subdirs-y += sio1007
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subdirs-y += kbc1100
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subdirs-y += mec1308
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subdirs-y += smscsuperio
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subdirs-y += sio1036
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subdirs-y += sch4037
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@ -0,0 +1,20 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Google Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c
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@ -0,0 +1,261 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Scope is \_SB.PCI0.LPCB
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Device (SIO) {
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OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
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Field (SIOA, ByteAcc, NoLock, Preserve)
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{
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SI2E, 8,
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SI2F, 8,
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}
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IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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SLDN, 8, /* Logical Device Number */
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Offset (0x30),
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SACT, 8, /* Activate */
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Offset (0x60),
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IO0H, 8, /* Base Address 0 MSB */
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IO0L, 8, /* Base Address 0 LSB */
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Offset (0x62),
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IO1H, 8, /* Base Address 1 MSB */
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IO1L, 8, /* Base Address 1 LSB */
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Offset (0x70),
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IQ00, 8, /* Interrupt Select */
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}
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Name (LPM1, 1) /* ACPI PM1 */
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Name (LEC1, 2) /* EC 1 */
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Name (LEC2, 3) /* EC 2 */
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Name (LSP1, 4) /* Serial Port */
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Name (LKBC, 7) /* Keyboard */
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Name (LEC0, 8) /* EC 0 */
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Name (LMBX, 9) /* Mailbox */
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Method (ENTR, 0, NotSerialized)
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{
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Store (0x55, SI2E)
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}
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Method (EXIT, 0, NotSerialized)
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{
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Store (0xaa, SI2E)
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}
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/* Parse activate register for an LDN */
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Method (ISEN, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (SACT, Local0)
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EXIT ()
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/* Check if it exists */
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If (LEqual (Local0, 0xFF))
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{
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Return (0x00)
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}
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/* Check if activated */
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If (LEqual (Local0, One))
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{
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Return (0x0F)
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}
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Else
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{
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Return (0x0D)
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}
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}
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/* Enable an LDN via the activate register */
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Method (SENA, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (One, SACT)
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EXIT ()
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}
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/* Disable an LDN via the activate register */
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Method (SDIS, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (Zero, SACT)
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EXIT ()
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}
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#ifdef SIO_ENABLE_SPM1
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Device (SPM1) {
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 1)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (LPM1))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08)
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})
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}
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#endif
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#ifdef SIO_ENABLE_SEC1
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Device (SEC1) {
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Name (_HID, EISAID ("PNP0C09"))
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Name (_UID, 2)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (LEC1))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04)
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})
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}
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#endif
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#ifdef SIO_ENABLE_SEC2
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Device (SEC2) {
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Name (_HID, EISAID ("PNP0C09"))
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Name (_UID, 3)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (LEC2))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04)
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})
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}
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#endif
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#ifdef SIO_ENABLE_SSP1
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Device (SSP1) {
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Name (_HID, EISAID ("PNP0501"))
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Name (_UID, 4)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (LSP1))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08)
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IRQNoFlags () {SIO_SSP1_IRQ}
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08)
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IRQNoFlags () {SIO_SSP1_IRQ}
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})
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}
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#endif
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#ifdef SIO_ENABLE_SKBC
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Device (SKBC) // Keyboard
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{
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Name (_HID, EISAID("PNP0303"))
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Name (_CID, EISAID("PNP030B"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (LKBC))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x60, 0x60, 0x01, 0x01)
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IO (Decode16, 0x64, 0x64, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, 0x60, 0x60, 0x01, 0x01)
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IO (Decode16, 0x64, 0x64, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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}
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#endif
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#ifdef SIO_ENABLE_SEC0
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Device (SEC0) {
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Name (_HID, EISAID ("PNP0C09"))
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Name (_UID, 8)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (LEC0))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04)
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})
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}
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#endif
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#ifdef SIO_ENABLE_SMBX
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Device (SMBX) // Mailbox
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{
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Name (_HID, EISAID("PNP0C02"))
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Name (_UID, 9)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (LMBX))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34)
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34)
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})
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}
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#endif
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}
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@ -0,0 +1,33 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SUPERIO_SMSC_MEC1308_CHIP_H
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#define SUPERIO_SMSC_MEC1308_CHIP_H
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#include <pc80/keyboard.h>
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#include <uart8250.h>
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struct chip_operations;
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extern struct chip_operations superio_smsc_mec1308_ops;
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struct superio_smsc_mec1308_config {
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struct pc_keyboard keyboard;
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};
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#endif
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define MEC1308_PM1 1
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#define MEC1308_EC1 2
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#define MEC1308_EC2 3
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#define MEC1308_UART 4
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#define MEC1308_KBC 7
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#define MEC1308_EC0 8
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#define MEC1308_MBX 9
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@ -0,0 +1,121 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* RAM driver for the SMSC MEC1308 Super I/O chip */
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <console/console.h>
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#include <device/smbus.h>
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#include <string.h>
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#include <bitops.h>
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#include <pc80/keyboard.h>
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#include <stdlib.h>
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#include "chip.h"
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#include "mec1308.h"
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#if CONFIG_HAVE_ACPI_RESUME
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#include <arch/acpi.h>
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#endif
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static void pnp_enter_conf_state(device_t dev)
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{
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outb(0x55, dev->path.pnp.port);
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}
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static void pnp_exit_conf_state(device_t dev)
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{
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outb(0xaa, dev->path.pnp.port);
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}
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static void mec1308_pnp_set_resources(device_t dev)
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{
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pnp_enter_conf_state(dev);
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pnp_set_resources(dev);
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pnp_exit_conf_state(dev);
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}
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static void mec1308_pnp_enable_resources(device_t dev)
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{
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pnp_enter_conf_state(dev);
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pnp_enable_resources(dev);
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pnp_exit_conf_state(dev);
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}
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static void mec1308_pnp_enable(device_t dev)
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{
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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if(dev->enabled) {
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pnp_set_enable(dev, 1);
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}
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else {
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pnp_set_enable(dev, 0);
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}
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pnp_exit_conf_state(dev);
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}
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static void mec1308_init(device_t dev)
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{
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struct superio_smsc_mec1308_config *conf = dev->chip_info;
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if (!dev->enabled)
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return;
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switch(dev->path.pnp.device) {
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case MEC1308_KBC:
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#if CONFIG_HAVE_ACPI_RESUME
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if (acpi_slp_type == 3)
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return;
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#endif
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pc_keyboard_init(&conf->keyboard);
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = mec1308_pnp_set_resources,
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.enable_resources = mec1308_pnp_enable_resources,
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.enable = mec1308_pnp_enable,
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.init = mec1308_init,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ &ops, MEC1308_PM1, PNP_IO0, { 0x7ff, 0 } },
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{ &ops, MEC1308_EC1, PNP_IO0, { 0x7ff, 0 } },
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{ &ops, MEC1308_EC2, PNP_IO0, { 0x7ff, 0 } },
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{ &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
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{ &ops, MEC1308_KBC, PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ },
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{ &ops, MEC1308_EC0, PNP_IO0, { 0x7ff, 0 } },
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{ &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } },
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};
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static void enable_dev(device_t dev)
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{
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pnp_enable_devices(dev, &pnp_ops,
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ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_smsc_mec1308_ops = {
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CHIP_NAME("SMSC MEC1308 EC SuperIO Interface")
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.enable_dev = enable_dev
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};
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