device/dram: add DDR4 RCD I2C access functions
Registering Clock Driver (RCD) is responsible for driving address and
control nets on RDIMM and LRDIMM applications. Its operation is
configurable by a set of Register Control Words (RCWs). There are two
ways of accessing RCWs: in-band on the memory channel as MRS commands
("MR7") or through I2C.
Access through I2C is generic, while MRS commands are passed to memory
controller registers in an implementation-specific way.
See JESD82-31 JEDEC standard for full details.
Change-Id: Ie4e6cfaeae16aba1853b33d527eddebadfbd3887
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Krystian Hebel
Felix Held
parent
757e0c1d40
commit
d3909e1793
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@ -9,7 +9,7 @@ ramstage-$(CONFIG_USE_DDR5) += ddr5.c
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romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
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ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
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romstage-$(CONFIG_USE_DDR4) += ddr4.c
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romstage-$(CONFIG_USE_DDR4) += ddr4.c rcd.c
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ramstage-$(CONFIG_USE_DDR4) += ddr4.c
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romstage-$(CONFIG_USE_DDR3) += ddr3.c
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@ -0,0 +1,218 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/dram/rcd.h>
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#include <endian.h>
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#include <lib.h>
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/**
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* Registering Clock Driver (RCD) is responsible for driving address and control
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* nets on RDIMM and LRDIMM applications. Its operation is configurable by a set
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* of Register Control Words (RCWs). There are two ways of accessing RCWs:
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* in-band on the memory channel as an MRS commands ("MR7") or through I2C.
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*
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* From JESD82-31: "For changes to the control word setting, (...) the
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* controller needs to wait tMRD after _the last control word access_, before
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* further access _to the DRAM_ can take place". MRS is passed to rank 0 of the
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* DRAM, but MR7 is reserved so it is ignored by DRAM. tMRD (8nCK) applies here,
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* unless longer delay is needed for RCWs which control the clock timing (see
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* JESD82-31 for list of such). This makes sense from DRAMs point of view,
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* however we are talking to the Registering Clock Driver (RCD), not DRAM. From
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* parts marked in the sentence above one may assume that only one delay at the
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* end is necessary and RCWs can be written back to back; however, in the same
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* document in table 141 tMRD is defined as "Number of clock cycles between two
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* control word accesses, MRS accesses, or any DRAM commands".
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*
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* I2C access to RCWs is required to support byte (8b), word (16b) and double
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* word (32b) write size. Bigger blocks are not required. Reads must always be
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* 32b, 32b-aligned blocks, even when reading just one RCW. RCD ignores the two
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* lowest bits so unaligned accesses would return shifted values. RCWs are
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* tightly packed in I2C space, so it is not possible to write just one 4b RCW
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* without writing its neighbor. This is especially important for F0RC06,
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* Command Space Control Word, as it is able to reset the state of RCD. For this
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* reason, the mentioned register has NOP command (all 1's). JESD82-31 does not
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* specify timeouts required for such multi-RCWs writes, or any other writes.
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* These are not MRS accesses, so it would be strange to apply those timeouts.
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* Perhaps only the registers that actually change the clock settings require
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* time to stabilize. On the other hand, I2C is relatively slow, so it is
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* possible that the write itself is long enough.
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*
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* RCD I2C address is 0xBx (or 0x58 + DIMM number, depending on convention), it
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* is located on the same bus as SPD. It uses a bus command encoding, see
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* section 3.3 in JESD82-31 for description of reading and writing register
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* values.
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*
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* This file includes only functions for access through I2C - it is generic,
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* while MRS commands are passed to memory controller registers in an
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* implementation specific way.
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*/
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#define RCD_CMD_BEGIN 0x80
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#define RCD_CMD_END 0x40
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#define RCD_CMD_PEC 0x10
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#define RCD_CMD_RD_DWORD 0x00
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#define RCD_CMD_WR_BYTE 0x04
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#define RCD_CMD_WR_WORD 0x08
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#define RCD_CMD_WR_DWORD 0x0C
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#define RCD_CMD_BUS_BYTE 0x00
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#define RCD_CMD_BUS_BLOCK 0x02
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/* Shorthand for block transfers */
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#define RCD_CMD_BLOCK (RCD_CMD_BEGIN | RCD_CMD_END | RCD_CMD_BUS_BLOCK)
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/* Excluding size of data */
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#define RCD_CMD_BYTES 4
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/* Use byte fields to get rid of endianness issues. */
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struct rcd_i2c_cmd {
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uint8_t cmd;
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uint8_t bytes; /* From next byte up to PEC (excluding) */
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uint8_t reserved;
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uint8_t devfun;
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uint8_t reg_h;
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uint8_t reg_l;
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union { /* Not used for reads, can use 1, 2 or 4 for writes */
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uint8_t bdata;
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uint32_t ddata;
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};
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/* Optional PEC */
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} __packed;
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#define RCD_STS_SUCCESS 0x01
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#define RCD_STS_INTERNAL_TARGET_ABORT 0x10
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/* Always 4 bytes data + status (for block commands) */
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#define RCD_RSP_BYTES 5
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struct rcd_i2c_rsp {
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uint8_t bytes; /* From next byte up to PEC (excluding) */
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uint8_t status;
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union {
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uint8_t bdata;
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uint32_t ddata;
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};
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/* Optional PEC */
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} __packed;
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/* Reads a register storing its value in the host's byte order. Returns non-zero on success. */
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static int rcd_readd(unsigned int bus, uint8_t slave, uint8_t reg, uint32_t *data)
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{
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struct i2c_msg seg[2];
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struct rcd_i2c_cmd cmd = {
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.cmd = RCD_CMD_BLOCK | RCD_CMD_RD_DWORD,
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.bytes = RCD_CMD_BYTES,
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.reg_l = reg
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};
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struct rcd_i2c_rsp rsp = { 0xaa, 0x55 };
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seg[0].flags = 0;
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seg[0].slave = slave;
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seg[0].buf = (uint8_t *)&cmd;
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seg[0].len = cmd.bytes + 2; /* + .cmd and .bytes fields */
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i2c_transfer(bus, seg, 1);
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seg[0].len = 1; /* Send just the command again */
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seg[1].flags = I2C_M_RD;
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seg[1].slave = slave;
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seg[1].buf = (uint8_t *)&rsp;
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seg[1].len = RCD_RSP_BYTES + 1; /* + .bytes field */
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i2c_transfer(bus, seg, ARRAY_SIZE(seg));
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/* Data is sent MSB to LSB, i.e. higher registers to lower. */
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*data = be32toh(rsp.ddata);
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return rsp.status == RCD_STS_SUCCESS;
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}
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static int rcd_writed(unsigned int bus, uint8_t slave, uint8_t reg, uint32_t data)
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{
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struct i2c_msg seg;
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struct rcd_i2c_cmd cmd = {
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.cmd = RCD_CMD_BLOCK | RCD_CMD_WR_DWORD,
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.bytes = RCD_CMD_BYTES + sizeof(data),
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.reg_l = reg,
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/* Data is sent MSB to LSB, i.e. higher registers to lower. */
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.ddata = htobe32(data)
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};
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seg.flags = 0;
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seg.slave = slave;
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seg.buf = (uint8_t *)&cmd;
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seg.len = cmd.bytes + 2; /* + .cmd and .bytes fields */
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return i2c_transfer(bus, &seg, 1);
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}
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static int rcd_writeb(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data)
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{
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struct i2c_msg seg;
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struct rcd_i2c_cmd cmd = {
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.cmd = RCD_CMD_BLOCK | RCD_CMD_WR_BYTE,
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.bytes = RCD_CMD_BYTES + sizeof(data),
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.reg_l = reg,
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.bdata = data
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};
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seg.flags = 0;
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seg.slave = slave;
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seg.buf = (uint8_t *)&cmd;
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seg.len = cmd.bytes + 2; /* + .cmd and .bytes fields */
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return i2c_transfer(bus, &seg, 1);
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}
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int rcd_write_reg(unsigned int bus, uint8_t slave, enum rcw_idx reg,
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uint8_t data)
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{
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if (reg < F0RC00_01 || reg > F0RCFx) {
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printk(BIOS_ERR, "Trying to write to illegal RCW %#2.2x\n",
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reg);
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return 0;
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}
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return rcd_writeb(bus, slave, reg, data);
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}
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int rcd_write_32b(unsigned int bus, uint8_t slave, enum rcw_idx reg,
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uint32_t data)
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{
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if (reg < F0RC00_01 || reg > F0RCFx) {
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printk(BIOS_ERR, "Trying to write to illegal RCW %#2.2x\n",
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reg);
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return 0;
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}
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if (reg & 3) {
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/*
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* RCD would silently mask out the lowest bits, assume that this
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* is not what caller wanted.
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*/
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printk(BIOS_ERR, "Unaligned RCW %#2.2x, aborting\n", reg);
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return 0;
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}
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return rcd_writed(bus, slave, reg, data);
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}
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void dump_rcd(unsigned int bus, u8 addr)
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{
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/* Can only read in 32b chunks */
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uint8_t buf[RCW_ALL_ALIGNED];
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int i;
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for (i = 0; i < RCW_ALL_ALIGNED; i += sizeof(uint32_t)) {
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uint32_t data;
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if (!rcd_readd(bus, addr, i, &data)) {
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printk(BIOS_ERR, "Failed to read RCD (%d-%02x) at offset %#2.2x\n",
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bus, addr, i);
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return;
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}
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/* We want to dump memory the way it's stored, so make sure it's in LE. */
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*(uint32_t *)&buf[i] = htole32(data);
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}
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printk(BIOS_DEBUG, "RCD dump for I2C address %#2.2x:\n", addr);
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hexdump(buf, sizeof(buf));
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}
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@ -0,0 +1,61 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef DEVICE_DRAM_RCD_H
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#define DEVICE_DRAM_RCD_H
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#include <types.h>
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#include <device/i2c_simple.h>
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#include <console/console.h>
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enum rcw_idx {
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VEN_ID_L,
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VEN_ID_H,
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DEV_ID_L,
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DEV_ID_H,
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REV_ID,
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RES_05,
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RES_06,
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RES_07,
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F0RC00_01,
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F0RC02_03,
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F0RC04_05,
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F0RC06_07,
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F0RC08_09,
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F0RC0A_0B,
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F0RC0C_0D,
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F0RC0E_0F,
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F0RC1x,
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F0RC2x,
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F0RC3x,
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F0RC4x,
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F0RC5x,
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F0RC6x,
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F0RC7x,
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F0RC8x,
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F0RC9x,
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F0RCAx,
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F0RCBx,
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F0RCCx,
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F0RCDx,
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F0RCEx,
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F0RCFx,
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RCW_ALL, /* Total num of bytes */
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RCW_ALL_ALIGNED /* Total num of bytes after aligning to 4B */
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};
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_Static_assert(RCW_ALL_ALIGNED % sizeof(uint32_t) == 0,
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"RCW_ALL_ALIGNED is not aligned");
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/* Write an 8-bit register. Returns the number of written bytes. */
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int rcd_write_reg(unsigned int bus, uint8_t slave, enum rcw_idx reg,
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uint8_t data);
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/* Write 32 bits of memory (i.e., four 8-bit registers, not 1 32-bit register, which would
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* involve byte swapping). Returns the number of written bytes. */
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int rcd_write_32b(unsigned int bus, uint8_t slave, enum rcw_idx reg,
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uint32_t data);
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/* Dump 32 bytes of RCD onto the screen. */
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void dump_rcd(unsigned int bus, uint8_t addr);
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#endif /* DEVICE_DRAM_RCD_H */
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