soc/amd/cezanne/makefile: order source files alphabetically

Change-Id: I4726ba4f19807adf872aaf04764cc19492febd59
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/cezanne/Makefile.inc

@@ -13,8 +13,8 @@ all-y		+= aoac.c
 
 bootblock-y	+= bootblock.c
 bootblock-y	+= early_fch.c
-bootblock-y	+= i2c.c
 bootblock-y	+= gpio.c
+bootblock-y	+= i2c.c
 bootblock-y	+= reset.c
 bootblock-y	+= uart.c
 
@@ -24,23 +24,23 @@ verstage_x86-y	+= reset.c
 verstage_x86-y	+= uart.c
 
 romstage-y	+= fsp_m_params.c
-romstage-y	+= i2c.c
 romstage-y	+= gpio.c
+romstage-y	+= i2c.c
 romstage-y	+= reset.c
 romstage-y	+= romstage.c
 romstage-y	+= uart.c
 
-ramstage-y	+= i2c.c
 ramstage-y	+= acpi.c
-ramstage-y	+= cppc.c
 ramstage-y	+= agesa_acpi.c
 ramstage-y	+= chip.c
+ramstage-y	+= cppc.c
 ramstage-y	+= cpu.c
 ramstage-y	+= data_fabric.c
 ramstage-y	+= fch.c
 ramstage-y	+= fsp_s_params.c
 ramstage-y	+= gpio.c
 ramstage-y	+= graphics.c
+ramstage-y	+= i2c.c
 ramstage-y	+= mca.c
 ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c