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soc/intel: Guard macro parameters in pm.h 

Guard against unintended operator precedence and associativity issues.

Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-02-19 16:08:36 +01:00 committed by Patrick Georgi
parent b0f52fb5bf
commit d3a65deb25
4 changed files with 9 additions and 9 deletions
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4
src/soc/intel/apollolake/include/soc/pm.h
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@ -120,7 +120,7 @@
#define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32
#define GPE0_STS(x) (0x20 + (x * 4))
#define GPE0_STS(x) (0x20 + ((x) * 4))
#define GPE0_A 0
#define GPE0_B 1
#define GPE0_C 2
@ -136,7 +136,7 @@
#define BATLOW_STS (1 << 10)
#define PCIE_GPE_STS (1 << 9)
#define SWGPE_STS (1 << 2)
#define GPE0_EN(x) (0x30 + (x * 4))
#define GPE0_EN(x) (0x30 + ((x) * 4))
#define ESPI_EN (1 << 20) /* This bit is present in GLK */
#define SATA_PME_EN (1 << 17)
#define SMB_WAK_EN (1 << 16)

4
src/soc/intel/broadwell/include/soc/pm.h
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@ -62,7 +62,7 @@
#define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32
#define GPE0_STS(x) (0x80 + (x * 4))
#define GPE0_STS(x) (0x80 + ((x) * 4))
#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
@ -78,7 +78,7 @@
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
#define GPE0_EN(x) (0x90 + (x * 4))
#define GPE0_EN(x) (0x90 + ((x) * 4))
#define WADT_en (1 << 18)
#define GP27_EN (1 << 16)
#define PME_B0_EN (1 << 13)

4
src/soc/intel/skylake/include/soc/pm.h
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@ -86,7 +86,7 @@
#define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32
#define GPE0_STS(x) (0x80 + (x * 4))
#define GPE0_STS(x) (0x80 + ((x) * 4))
#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
#define GPE_95_64 2 /* 0x88/0x98 = GPE[95:64] */
@ -105,7 +105,7 @@
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
#define GPE0_EN(x) (0x90 + (x * 4))
#define GPE0_EN(x) (0x90 + ((x) * 4))
#define WADT_EN (1 << 18)
#define LAN_WAK_EN (1 << 16)
#define GPIO_T2_EN (1 << 15)

6
src/soc/intel/xeon_sp/include/soc/pm.h
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@ -66,8 +66,8 @@
#define PM2_CNT 0x50
#define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32
#define GPE0_STS(x) (0x80 + (x * 4))
#define GPE0_EN(x) (0x90 + (x * 4))
#define GPE0_STS(x) (0x80 + ((x) * 4))
#define GPE0_EN(x) (0x90 + ((x) * 4))
#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
#define GPE_STS_RSVD GPE_STD
#define GPIO_T2_STS (1 << 15)
@ -76,7 +76,7 @@
#define PCI_EXP_STS (1 << 9)
#define SMB_WAK_STS (1 << 7)
#define TCOSCI_STS (1 << 6)
#define GPE0_EN(x) (0x90 + (x * 4))
#define GPE0_EN(x) (0x90 + ((x) * 4))
#define GPIO_T2_EN (1 << 15)
#define ESPI_EN (1 << 14)
#define PME_B0_EN (1 << 13)