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baytrail: Fix hdmi audio choppy issue 

Disable VC setting for HDA so hdmi audio choppy issue will be eliminated.
Change HDA initialize steps to sync with UEFI reference code.

BUG=chrome-os-partner:25651
BRANCH=Baytrail
TEST=Does not have choppy noise during video playing

Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com>

Original-Change-Id: I45d49123d369b7d075776215e709af5801ea696d
Original-Reviewed-on: https://chromium-review.googlesource.com/186024
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Tested-by: Benson Leung <bleung@chromium.org>
Original-Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
(cherry picked from commit 9f725a40f77cd684b2e230bd226d78d87b56e73b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4fc10a161e5996e14d4823491fb62a7beff39bcc
Reviewed-on: http://review.coreboot.org/9297
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kein Yuan 2014-02-11 17:40:31 -08:00 committed by Marc Jones
parent 2088571f56
commit d3b40bfc2d
2 changed files with 13 additions and 5 deletions
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5
src/soc/intel/baytrail/hda.c
View File

@ -31,11 +31,6 @@
#include <baytrail/ramstage.h> #include <baytrail/ramstage.h>
static const struct reg_script init_ops[] = { static const struct reg_script init_ops[] = {
/* Set up VC0 and VC1. */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x24, 0x80000019),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x28, 0x81000022),
/* Enable VCi */
REG_PCI_WRITE32(0x120, 0x81000022),
/* Enable no snoop traffic. */ /* Enable no snoop traffic. */
REG_PCI_OR16(0x78, 1 << 11), REG_PCI_OR16(0x78, 1 << 11),
/* Configure HDMI codec connection. */ /* Configure HDMI codec connection. */

13
src/soc/intel/common/hda_verb.c
View File

@ -70,6 +70,19 @@ int hda_codec_detect(u8 *base)
/* Write back the value once reset bit is set. */ /* Write back the value once reset bit is set. */
write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
/* Clear the "State Change Status Register" STATESTS bits
* for each of the "SDIN Stat Change Status Flag"
*/
write8(base + HDA_STATESTS_REG, 0xf);
/* Turn off the link and poll RESET# bit until it reads back as 0 */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0)
goto no_codec;
/* Turn on the link and poll RESET# bit until it reads back as 1 */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/ /* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + HDA_STATESTS_REG); reg8 = read8(base + HDA_STATESTS_REG);
reg8 &= 0x0f; reg8 &= 0x0f;