Fall back to pre-broken settings and setup for GX2.
We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
ae3cbe951b
commit
d3ba4aaa24
|
|
@ -9,8 +9,7 @@
|
|||
/* **/
|
||||
/* ***************************************************************************/
|
||||
static void
|
||||
BIST(void)
|
||||
{
|
||||
BIST(void){
|
||||
int msrnum;
|
||||
msr_t msr;
|
||||
|
||||
|
|
@ -25,8 +24,8 @@ BIST(void)
|
|||
msrnum = CPU_DM_BIST;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
outb(POST_CPU_DM_BIST_FAILURE , 0x80); /* 0x29*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
msr.lo &= 0x0F3FF0000;
|
||||
if (msr.lo != 0xfeff0000)
|
||||
goto BISTFail;
|
||||
|
|
@ -42,115 +41,108 @@ BIST(void)
|
|||
msrnum = CPU_FP_UROM_BIST;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
|
||||
inb(0x80); /* IO delay*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
|
||||
inb(0x80); /* IO delay*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
while ((msr.lo&0x884) != 0x884)
|
||||
msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
|
||||
msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
|
||||
if ((msr.lo&0x642) != 0x642)
|
||||
goto BISTFail;
|
||||
msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
|
||||
|
||||
msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
|
||||
msrnum = CPU_FP_UROM_BIST;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
||||
/* BTB*/
|
||||
msr.lo = 0x000000303;
|
||||
msr.hi = 0x000000000;
|
||||
msrnum = CPU_PF_BTBRMA_BIST;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
outb(POST_CPU_BTB_BIST_FAILURE, 0x80); /* 0x8A*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
|
||||
msr = rdmsr(msrnum); /* read back for pass fail*/
|
||||
if ((msr.lo & 0x3030) != 0x3030)
|
||||
goto BISTFail;
|
||||
|
||||
return;
|
||||
|
||||
BISTFail:
|
||||
print_err("BIST failed!\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
void BTM_enable(void)
|
||||
{
|
||||
int msrnum;
|
||||
msr_t msr;
|
||||
/* Set Diagnostic Mode */
|
||||
msrnum = CPU_GLD_MSR_DIAG;
|
||||
msr.hi = 0;
|
||||
msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set up GLCP to grab BTM data.*/
|
||||
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
|
||||
msr.hi = 0x0;
|
||||
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
|
||||
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
|
||||
|
||||
/* ;Turn off debug clock*/
|
||||
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
|
||||
msr.lo = 0x00; /* No clock*/
|
||||
msr.hi = 0x00;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* ;Set debug clock to CPU*/
|
||||
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
|
||||
msr.lo = 0x01; /* CPU CLOCK*/
|
||||
msr.hi = 0x00;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* ;Set fifo ctl to BTM bits wide*/
|
||||
msrnum = 0x04C00005E; /* FIFO_CTL*/
|
||||
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit,
|
||||
* 01= 32 bit, 00 = 16bit),
|
||||
* Bit [23:21] are position (100 = CPU downto0)*/
|
||||
wrmsr(msrnum, msr); /* */
|
||||
/* Bit [19] sets it up in slow data mode.*/
|
||||
|
||||
/* ;enable fifo loading - BTM sizing will constrain*/
|
||||
/* ; only valid BTM packets to load - this action should always be on*/
|
||||
msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
|
||||
msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
|
||||
msr.hi = 0x000000000; /* */
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* ;start storing diag data in the fifo*/
|
||||
msrnum = 0x04C00005F; /* DIAG CTL*/
|
||||
msr.lo = 0x080000000; /* enable actions*/
|
||||
msr.hi = 0x000000000;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set up delay on data lines, so that the hold time*/
|
||||
/* is 1 ns.*/
|
||||
msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
|
||||
msr.lo = 0x082b5ad68;
|
||||
msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set up DF to output diag information on DF pins.*/
|
||||
msrnum = DF_GLD_MSR_MASTER_CONF;
|
||||
msr.lo = 0x0220;
|
||||
msr.hi = 0;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
|
||||
msr.hi = 0x0;
|
||||
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
|
||||
wrmsr(msrnum, msr);
|
||||
/* end of code for BTM */
|
||||
}
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* * cpuRegInit*/
|
||||
/* ***************************************************************************/
|
||||
void
|
||||
cpuRegInit (void)
|
||||
{
|
||||
cpuRegInit (void){
|
||||
int msrnum;
|
||||
msr_t msr;
|
||||
/* Turn on BTM for early debug based on setup. */
|
||||
/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
|
||||
{
|
||||
BTM_enable();
|
||||
/* Set Diagnostic Mode */
|
||||
msrnum = CPU_GLD_MSR_DIAG;
|
||||
msr.hi = 0;
|
||||
msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set up GLCP to grab BTM data.*/
|
||||
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
|
||||
msr.hi = 0x0;
|
||||
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
|
||||
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
|
||||
|
||||
/* ;Turn off debug clock*/
|
||||
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
|
||||
msr.lo = 0x00; /* No clock*/
|
||||
msr.hi = 0x00;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* ;Set debug clock to CPU*/
|
||||
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
|
||||
msr.lo = 0x01; /* CPU CLOCK*/
|
||||
msr.hi = 0x00;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* ;Set fifo ctl to BTM bits wide*/
|
||||
msrnum = 0x04C00005E; /* FIFO_CTL*/
|
||||
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
|
||||
wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
|
||||
/* Bit [19] sets it up in slow data mode.*/
|
||||
|
||||
/* ;enable fifo loading - BTM sizing will constrain*/
|
||||
/* ; only valid BTM packets to load - this action should always be on*/
|
||||
|
||||
msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
|
||||
msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
|
||||
msr.hi = 0x000000000; /* */
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* ;start storing diag data in the fifo*/
|
||||
msrnum = 0x04C00005F; /* DIAG CTL*/
|
||||
msr.lo = 0x080000000; /* enable actions*/
|
||||
msr.hi = 0x000000000;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set up delay on data lines, so that the hold time*/
|
||||
/* is 1 ns.*/
|
||||
msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
|
||||
msr.lo = 0x082b5ad68;
|
||||
msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set up DF to output diag information on DF pins.*/
|
||||
msrnum = DF_GLD_MSR_MASTER_CONF;
|
||||
msr.lo = 0x0220;
|
||||
msr.hi = 0;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
|
||||
msr.hi = 0x0;
|
||||
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
|
||||
wrmsr(msrnum, msr);
|
||||
/* end of code for BTM */
|
||||
}
|
||||
|
||||
/* Enable Suspend on Halt*/
|
||||
|
|
@ -172,32 +164,49 @@ cpuRegInit (void)
|
|||
msr.lo = 0x00000603C;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Enable CIS mode C */
|
||||
|
||||
/* Only do this if we are building for 5535*/
|
||||
/* */
|
||||
/* FooGlue Setup*/
|
||||
/* */
|
||||
#if 1
|
||||
/* Enable CIS mode B in FooGlue*/
|
||||
msrnum = MSR_FG + 0x10;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~3;
|
||||
msr.lo |= 2;
|
||||
msr.lo |= 2; /* ModeB*/
|
||||
wrmsr(msrnum, msr);
|
||||
#endif
|
||||
|
||||
/* Disable DOT PLL. Graphics init will enable it if needed.*/
|
||||
/* */
|
||||
/* Disable DOT PLL. Graphics init will enable it if needed.*/
|
||||
/* */
|
||||
msrnum = GLCP_DOTPLL;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= DOTPPL_LOWER_PD_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Enable RSDC and other SMM instructions */
|
||||
/* */
|
||||
/* Enable RSDC*/
|
||||
/* */
|
||||
msrnum = 0x1301 ;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= 0x08;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* BIST*/
|
||||
|
||||
/* */
|
||||
/* BIST*/
|
||||
/* */
|
||||
/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
|
||||
{
|
||||
//BIST();
|
||||
// BIST();
|
||||
}
|
||||
|
||||
/* Enable BTB*/
|
||||
|
||||
/* */
|
||||
/* Enable BTB*/
|
||||
/* */
|
||||
/* I hate to put this check here but it doesn't really work in cpubug.asm*/
|
||||
msrnum = MSR_GLCP+0x17;
|
||||
msr = rdmsr(msrnum);
|
||||
|
|
@ -208,7 +217,9 @@ cpuRegInit (void)
|
|||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
||||
/* FPU impercise exceptions bit*/
|
||||
/* */
|
||||
/* FPU impercise exceptions bit*/
|
||||
/* */
|
||||
/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
|
||||
{
|
||||
msrnum = CPU_FPU_MSR_MODE;
|
||||
|
|
@ -217,7 +228,9 @@ cpuRegInit (void)
|
|||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
||||
/* Cache Overides*/
|
||||
/* */
|
||||
/* Cache Overides*/
|
||||
/* */
|
||||
/* Allow NVRam to override DM Setup*/
|
||||
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
|
||||
{
|
||||
|
|
@ -237,6 +250,9 @@ cpuRegInit (void)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * MTestPinCheckBX*/
|
||||
|
|
@ -246,8 +262,7 @@ cpuRegInit (void)
|
|||
/* **/
|
||||
/* ***************************************************************************/
|
||||
static void
|
||||
MTestPinCheckBX (void)
|
||||
{
|
||||
MTestPinCheckBX (void){
|
||||
int msrnum;
|
||||
msr_t msr;
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ static void vsm_end_post_smi(void)
|
|||
__asm__ volatile (
|
||||
"push %ax\n"
|
||||
"mov $0x5000, %ax\n"
|
||||
/* smint */
|
||||
".byte 0x0f, 0x38\n"
|
||||
"pop %ax\n"
|
||||
);
|
||||
|
|
@ -25,7 +24,9 @@ static void model_gx2_init(device_t dev)
|
|||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
|
||||
/* send SYS_END_OF_POST to VSM */
|
||||
/* Enable the local cpu apics */
|
||||
//setup_lapic();
|
||||
|
||||
vsm_end_post_smi();
|
||||
|
||||
printk_debug("model_gx2_init DONE\n");
|
||||
|
|
|
|||
|
|
@ -1,13 +1,20 @@
|
|||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * StartTimer1*/
|
||||
/* **/
|
||||
/* * Entry: none*/
|
||||
/* * Exit: Starts Timer 1 for port 61 use*/
|
||||
/* * Destroys: Al,*/
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
void
|
||||
StartTimer1(void)
|
||||
{
|
||||
StartTimer1(void){
|
||||
outb(0x56, 0x43);
|
||||
outb(0x12, 0x41);
|
||||
}
|
||||
|
||||
void
|
||||
SystemPreInit(void)
|
||||
{
|
||||
SystemPreInit(void){
|
||||
|
||||
/* they want a jump ... */
|
||||
__asm__("jmp .+2\ninvd\njmp.+2\n");
|
||||
|
|
|
|||
|
|
@ -469,18 +469,18 @@
|
|||
/* This is chip specific!*/
|
||||
#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
|
||||
#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
|
||||
#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
|
||||
#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/
|
||||
#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
|
||||
#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/
|
||||
#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO*/
|
||||
#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO*/
|
||||
|
||||
#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/
|
||||
#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/
|
||||
#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/
|
||||
#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/
|
||||
#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/
|
||||
#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/
|
||||
#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/
|
||||
#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/
|
||||
#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/
|
||||
#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/
|
||||
|
||||
/* definitions that are "once you are mostly up, start VSA" type things */
|
||||
#define SMM_OFFSET 0x40400000
|
||||
|
|
|
|||
|
|
@ -102,6 +102,22 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
|||
#include "northbridge/amd/gx2/pll_reset.c"
|
||||
#include "cpu/amd/model_gx2/cpureginit.c"
|
||||
#include "cpu/amd/model_gx2/syspreinit.c"
|
||||
static void msr_init(void)
|
||||
{
|
||||
/* total physical memory */
|
||||
__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
|
||||
|
||||
/* traditional memory 0kB-512kB, 512kB-1MB */
|
||||
__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
|
||||
__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
|
||||
|
||||
__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
|
||||
__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
|
||||
|
||||
/* put code in northbridge[init].c here */
|
||||
}
|
||||
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl [] = {
|
||||
|
|
@ -109,6 +125,8 @@ static void main(unsigned long bist)
|
|||
};
|
||||
|
||||
SystemPreInit();
|
||||
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
|
@ -122,6 +140,8 @@ static void main(unsigned long bist)
|
|||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
msr_init();
|
||||
|
||||
/* Check all of memory */
|
||||
//ram_check(0x00000000, 640*1024);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -133,7 +133,6 @@ chip northbridge/amd/gx2
|
|||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
chip southbridge/amd/cs5536
|
||||
register "enable_gpio0_inta" = "1"
|
||||
device pci d.0 on end # Realtek 8139 LAN
|
||||
device pci f.0 on end # ISA Bridge
|
||||
device pci f.2 on end # IDE Controller
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@
|
|||
* FIXME -- make this configurable
|
||||
*/
|
||||
#define RAMADJUSTMB 9
|
||||
/*
|
||||
*/
|
||||
|
||||
/* todo: add a resource record. We don't do this here because this may be called when
|
||||
* very little of the platform is actually working.
|
||||
|
|
@ -50,15 +52,194 @@ sizeram(void)
|
|||
return sizem;
|
||||
}
|
||||
|
||||
|
||||
/* here is programming for the various MSRs.*/
|
||||
#define IM_QWAIT 0x100000
|
||||
|
||||
#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
|
||||
#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
|
||||
|
||||
/* these are the 8-bit attributes for controlling RCONF registers */
|
||||
#define CACHE_DISABLE (1<<0)
|
||||
#define WRITE_ALLOCATE (1<<1)
|
||||
#define WRITE_PROTECT (1<<2)
|
||||
#define WRITE_THROUGH (1<<3)
|
||||
#define WRITE_COMBINE (1<<4)
|
||||
#define WRITE_SERIALIZE (1<<5)
|
||||
|
||||
/* ram has none of this stuff */
|
||||
#define RAM_PROPERTIES (0)
|
||||
#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
|
||||
#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_THROUGH|CACHE_DISABLE)
|
||||
#define MSR_WS_CD_DEFAULT (0x21212121)
|
||||
|
||||
/* 1810-1817 give you 8 registers with which to program protection regions */
|
||||
/* the are region configuration range registers, or RRCF */
|
||||
/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
|
||||
/* so no left-shift needed for top or base */
|
||||
#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
|
||||
#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
|
||||
|
||||
/* build initializer for P2D MSR */
|
||||
#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
|
||||
#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
|
||||
#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
|
||||
#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
|
||||
#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
|
||||
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
|
||||
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
|
||||
|
||||
|
||||
|
||||
struct msr_defaults {
|
||||
int msr_no;
|
||||
msr_t msr;
|
||||
} msr_defaults [] = {
|
||||
{0x1700, {.hi = 0, .lo = IM_QWAIT}},
|
||||
{0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}},
|
||||
/* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
|
||||
/* for 180a, for now, we assume VSM will configure it */
|
||||
/* 180b is left at reset value,a0000-bffff is non-cacheable */
|
||||
/* 180c, c0000-dffff is set to write serialize and non-cachable */
|
||||
/* oops, 180c will be set by cpu bug handling in cpubug.c */
|
||||
//{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
|
||||
/* 180d is left at default, e0000-fffff is non-cached */
|
||||
|
||||
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
|
||||
/* we will not set 0x180f, the DMM,yet */
|
||||
//{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
|
||||
//{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
|
||||
//{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
|
||||
//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
|
||||
/* now for GLPCI routing */
|
||||
/* GLIU0 */
|
||||
P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
|
||||
P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
|
||||
P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0x3),
|
||||
/* GLIU1 */
|
||||
P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
|
||||
P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
|
||||
P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0x3),
|
||||
{0}
|
||||
};
|
||||
|
||||
|
||||
static int
|
||||
setup_gx2_cache(void)
|
||||
{
|
||||
msr_t msr;
|
||||
unsigned long long val;
|
||||
int sizembytes, sizereg;
|
||||
|
||||
sizembytes = sizeram();
|
||||
printk_debug("enable_cache: enable for %dm bytes\n", sizembytes);
|
||||
/* build up the rconf word. */
|
||||
/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
|
||||
/* set romrp */
|
||||
val = ((unsigned long long) ROM_PROPERTIES) << 56;
|
||||
/* make rom base useful for 1M roms */
|
||||
/* Flash base address -- sized for 1/2M for now*/
|
||||
val |= ((unsigned long long) 0xfff800)<<36;
|
||||
/* set the devrp properties */
|
||||
val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
|
||||
/* sigh. Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
|
||||
/* yank off 8M for frame buffer and 1M for VSA */
|
||||
sizembytes -= RAMADJUSTMB;
|
||||
sizereg = sizembytes;
|
||||
sizereg *= 0x100000;
|
||||
sizereg >>= 12;
|
||||
sizereg <<= 8;
|
||||
val |= sizereg;
|
||||
val |= RAM_PROPERTIES;
|
||||
msr.lo = val;
|
||||
msr.hi = (val >> 32);
|
||||
printk_debug("msr will be set to %x:%x\n", msr.hi, msr.lo);
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
enable_cache();
|
||||
wbinvd();
|
||||
return sizembytes;
|
||||
}
|
||||
|
||||
#define SMM_OFFSET 0x40400000
|
||||
#define SMM_SIZE 256
|
||||
|
||||
/* we have to do this here. We have not found a nicer way to do it */
|
||||
void
|
||||
setup_gx2(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long tmp, tmp2, tmp3;
|
||||
msr_t msr;
|
||||
unsigned long sizem, membytes;
|
||||
|
||||
sizem = setup_gx2_cache();
|
||||
|
||||
membytes = sizem * 1048576;
|
||||
#if 0
|
||||
/* we need to set 0x10000028 and 0x40000029 */
|
||||
printk_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
|
||||
msr.hi = 0x20000000 | membytes>>24;
|
||||
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
|
||||
wrmsr(0x10000028, msr);
|
||||
msr.hi = 0x20000000 | membytes>>24;
|
||||
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
|
||||
wrmsr(0x40000029, msr);
|
||||
msr = rdmsr(0x10000028);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
|
||||
msr = rdmsr(0x40000029);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
|
||||
|
||||
|
||||
/* fixme: SMM MSR 0x10000026 and 0x400000023 */
|
||||
/* calculate the OFFSET field */
|
||||
tmp = membytes - SMM_OFFSET;
|
||||
tmp >>= 12;
|
||||
tmp <<= 8;
|
||||
tmp |= 0x20000000;
|
||||
tmp |= (SMM_OFFSET >> 24);
|
||||
|
||||
/* calculate the PBASE and PMASK fields */
|
||||
tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
|
||||
tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
|
||||
msr.hi = tmp;
|
||||
msr.lo = tmp2;
|
||||
wrmsr(0x10000026, msr);
|
||||
#else
|
||||
msr.hi = 0x2000000f;
|
||||
msr.lo = 0xfbf00100;
|
||||
wrmsr(0x10000028, msr);
|
||||
msr = rdmsr(0x10000028);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
|
||||
wrmsr(0x40000029, msr);
|
||||
msr = rdmsr(0x40000029);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
|
||||
|
||||
msr.hi = 0x2cfbc040;
|
||||
msr.lo = 0x400fffc0;
|
||||
wrmsr(0x10000026, msr);
|
||||
msr = rdmsr(0x10000026);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
|
||||
|
||||
msr.hi = 0x22fffc02;
|
||||
msr.lo = 0x10ffbf00;
|
||||
wrmsr(0x1808, msr);
|
||||
msr = rdmsr(0x1808);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
|
||||
#endif
|
||||
/* now do the default MSR values */
|
||||
for(i = 0; msr_defaults[i].msr_no; i++) {
|
||||
msr_t msr;
|
||||
wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);
|
||||
msr = rdmsr(msr_defaults[i].msr_no);
|
||||
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
|
||||
}
|
||||
}
|
||||
|
||||
static void enable_shadow(device_t dev)
|
||||
{
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static void northbridge_init(device_t dev)
|
||||
|
|
@ -237,7 +418,7 @@ static void enable_dev(struct device *dev)
|
|||
northbridgeinit();
|
||||
cpubug();
|
||||
chipsetinit();
|
||||
setup_gx2_cache();
|
||||
setup_gx2();
|
||||
/* do this here for now -- this chip really breaks our device model */
|
||||
setup_realmode_idt();
|
||||
do_vsmbios();
|
||||
|
|
|
|||
|
|
@ -22,39 +22,27 @@ struct gliutable {
|
|||
};
|
||||
|
||||
struct gliutable gliu0table[] = {
|
||||
/* 0x00000-0x7FFFF to MC */
|
||||
{.desc_name = MSR_GLIU0_BASE1, .desc_type = BM, .hi = MSR_MC + 0x0,.lo = 0xFFF80},
|
||||
/* 0x80000-0x9ffff to Mc */
|
||||
{.desc_name = MSR_GLIU0_BASE2, .desc_type = BM, .hi = MSR_MC + 0x0,.lo = (0x80 << 20) + 0xFFFE0},
|
||||
/* 0xc0000-0xfffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
|
||||
{.desc_name = MSR_GLIU0_SHADOW, .desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo= 0x03},
|
||||
/* Catch and fix dynamicly.*/
|
||||
{.desc_name = MSR_GLIU0_SYSMEM, .desc_type = R_SYSMEM, .hi = MSR_MC, .lo= 0x0},
|
||||
/* Catch and fix dynamicly.*/
|
||||
{.desc_name = MSR_GLIU0_DMM, .desc_type = BMO_DMM, .hi = MSR_MC,.lo = 0x0},
|
||||
/* Catch and fix dynamicly.*/
|
||||
{.desc_name = MSR_GLIU0_SMM, .desc_type = BMO_SMM, .hi = MSR_MC,.lo = 0x0},
|
||||
{.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER, .hi = 0x0, .lo = GL0_CPU},
|
||||
{.desc_name = GL_END, .desc_type = GL_END, .hi = 0x0, .lo = 0x0},
|
||||
{.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
|
||||
{.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
|
||||
{.desc_name=MSR_GLIU0_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
|
||||
{.desc_name=MSR_GLIU0_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
|
||||
{.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
|
||||
{.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
|
||||
{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
|
||||
{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
|
||||
};
|
||||
|
||||
|
||||
struct gliutable gliu1table[] = {
|
||||
/* 0x00000-0x7FFFF to GLIU0 */
|
||||
{.desc_name = MSR_GLIU1_BASE1, .desc_type = BM, .hi = MSR_GL0 + 0x0,.lo= 0x0FFF80},
|
||||
/* 0x80000-0x9ffff to GLIU0 */
|
||||
{.desc_name = MSR_GLIU1_BASE2, .desc_type = BM, .hi = MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},
|
||||
/* 0xc0000-0xfffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
|
||||
{.desc_name = MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03},
|
||||
/* Cat0xc and fix dynamicly.*/
|
||||
{.desc_name = MSR_GLIU1_SYSMEM,. desc_type = R_SYSMEM,.hi= MSR_GL0,.lo= 0x0},
|
||||
/* Cat0xc and fix dynamicly.*/
|
||||
{.desc_name = MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0},
|
||||
/* Cat0xc and fix dynamicly.*/
|
||||
{.desc_name = MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0},
|
||||
{.desc_name = GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
|
||||
/* FooGlue FPU 0xF0*/
|
||||
{.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0},
|
||||
{.desc_name = GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
|
||||
{.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
|
||||
{.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/
|
||||
{.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03},/* C0000-Fffff split to MC and PCI (sub decode)*/
|
||||
{.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
|
||||
{.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
|
||||
{.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
|
||||
{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
|
||||
{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/
|
||||
{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
|
||||
};
|
||||
|
||||
struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
|
||||
|
|
@ -270,15 +258,16 @@ SMMGL1Init(struct gliutable *gl) {
|
|||
}
|
||||
|
||||
static void
|
||||
GLIUInit(struct gliutable *gl)
|
||||
{
|
||||
GLIUInit(struct gliutable *gl){
|
||||
|
||||
while (gl->desc_type != GL_END){
|
||||
switch(gl->desc_type){
|
||||
default:
|
||||
printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported type: ",
|
||||
__FUNCTION__, gl->desc_name, gl->desc_type, gl->hi, gl->hi);
|
||||
printk_err("Must be %x, %x, %x, %x, %x, or %x\n",
|
||||
SC_SHADOW,R_SYSMEM,BMO_DMM, BM_DMM, BMO_SMM,BM_SMM);
|
||||
printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported type: ", __FUNCTION__,
|
||||
gl->desc_name, gl->desc_type, gl->hi, gl->hi);
|
||||
printk_err("Must be %x, %x, %x, %x, %x, or %x\n", SC_SHADOW,R_SYSMEM,BMO_DMM,
|
||||
BM_DMM, BMO_SMM,BM_SMM);
|
||||
|
||||
case SC_SHADOW: /* Check for a Shadow entry*/
|
||||
ShadowInit(gl);
|
||||
break;
|
||||
|
|
@ -287,7 +276,7 @@ GLIUInit(struct gliutable *gl)
|
|||
SysmemInit(gl);
|
||||
break;
|
||||
|
||||
case BMO_DMM: /* check for a DMM entry*/
|
||||
case BMO_DMM: /* check for a DMM entry*/
|
||||
DMMGL0Init(gl);
|
||||
break;
|
||||
|
||||
|
|
@ -555,22 +544,18 @@ northbridgeinit(void)
|
|||
int i;
|
||||
printk_debug("Enter %s\n", __FUNCTION__);
|
||||
|
||||
/*
|
||||
for(i = 0; gliutables[i]; i++)
|
||||
GLIUInit(gliutables[i]);
|
||||
|
||||
GeodeLinkPriority();
|
||||
|
||||
|
||||
*/
|
||||
/* Now that the descriptor to memory is set up.*/
|
||||
/* The memory controller needs one read to synch it's lines before it can be used.*/
|
||||
i = *(int *) 0;
|
||||
|
||||
GLPCIInit();
|
||||
/*
|
||||
ClockGatingInit();
|
||||
*/
|
||||
__asm__("FINIT\n");
|
||||
/* CPUBugsFix -- called elsewhere */
|
||||
printk_debug("Exit %s\n", __FUNCTION__);
|
||||
|
|
|
|||
|
|
@ -4,175 +4,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
{
|
||||
}
|
||||
|
||||
/* here is programming for the various MSRs.*/
|
||||
#define IM_QWAIT 0x100000
|
||||
|
||||
#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
|
||||
#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
|
||||
|
||||
/* these are the 8-bit attributes for controlling RCONF registers */
|
||||
#define CACHE_DISABLE (1<<0)
|
||||
#define WRITE_ALLOCATE (1<<1)
|
||||
#define WRITE_PROTECT (1<<2)
|
||||
#define WRITE_THROUGH (1<<3)
|
||||
#define WRITE_COMBINE (1<<4)
|
||||
#define WRITE_SERIALIZE (1<<5)
|
||||
|
||||
/* ram has none of this stuff */
|
||||
#define RAM_PROPERTIES (0)
|
||||
#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
|
||||
#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_THROUGH|CACHE_DISABLE)
|
||||
#define MSR_WS_CD_DEFAULT (0x21212121)
|
||||
|
||||
/* 1810-1817 give you 8 registers with which to program protection regions */
|
||||
/* the are region configuration range registers, or RRCF */
|
||||
/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
|
||||
/* so no left-shift needed for top or base */
|
||||
#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
|
||||
#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
|
||||
|
||||
/* build initializer for P2D MSR */
|
||||
#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}
|
||||
#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}
|
||||
#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}
|
||||
#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}
|
||||
#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}
|
||||
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}
|
||||
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}
|
||||
|
||||
struct msr_defaults {
|
||||
int msr_no;
|
||||
unsigned long hi, lo;
|
||||
};
|
||||
|
||||
|
||||
const struct msr_defaults msr_defaults [] = {
|
||||
{0x1700, .hi = 0, .lo = IM_QWAIT},
|
||||
{0x1800, .hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES},
|
||||
/* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
|
||||
/* for 180a, for now, we assume VSM will configure it */
|
||||
/* 180b is left at reset value,a0000-bffff is non-cacheable */
|
||||
/* 180c, c0000-dffff is set to write serialize and non-cachable */
|
||||
/* oops, 180c will be set by cpu bug handling in cpubug.c */
|
||||
//{0x180c, .hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT},
|
||||
/* 180d is left at default, e0000-fffff is non-cached */
|
||||
|
||||
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
|
||||
/* we will not set 0x180f, the DMM,yet */
|
||||
//{0x1810, .hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)},
|
||||
//{0x1811, .hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)},
|
||||
//{0x1812, .hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)},
|
||||
//{0x1813, .hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)},
|
||||
|
||||
/* GeodeLink Routing */
|
||||
/* GLIU0 */
|
||||
/* Traditional Memory 0kB-512kB goes to GLIU port 1, Memory Controller */
|
||||
P2D_BM(0x10000020, 0x1, 0x0, 0x00000, 0xfff80),
|
||||
/* Traditional Memory 512kB-1MB goes to GLIU port 1, Memory Controller */
|
||||
P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
|
||||
/* Extended Memory, 0xC0000-0x100000, disable write,
|
||||
* enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
|
||||
* goest to GLIU Port 1, Memory Controller */
|
||||
P2D_SC(0x1000002c, 0x1, 0x0, 0x0000, 0xff03, 0x3),
|
||||
/* GLIU1 */
|
||||
/* Traditional Memory 0kB-512kB goes to GLIU port 1, link to GLIU0 */
|
||||
P2D_BM(0x40000020, 0x1, 0x0, 0x00000, 0xfff80),
|
||||
/* Traditional Memory 512kB-1MB goes to GLIU port 1, link to GLIU0 */
|
||||
P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
|
||||
/* Extended Memory, 0xC0000-0x100000, disable write,
|
||||
* enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
|
||||
* goest to GLIU Port 1, Memory Controller */
|
||||
P2D_SC(0x4000002d, 0x1, 0x0, 0x0000, 0xff03, 0x3),
|
||||
/* end of table */
|
||||
{0}
|
||||
};
|
||||
|
||||
#define SMM_OFFSET 0x40400000
|
||||
#define SMM_SIZE 256
|
||||
|
||||
|
||||
void
|
||||
setup_gx2(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long tmp, tmp2, tmp3;
|
||||
msr_t msr;
|
||||
unsigned long sizem, membytes;
|
||||
#if 0
|
||||
sizem = setup_gx2_cache();
|
||||
|
||||
membytes = sizem * 1048576;
|
||||
|
||||
/* we need to set 0x10000028 and 0x40000029 */
|
||||
//print_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
|
||||
msr.hi = 0x20000000 | membytes>>24;
|
||||
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
|
||||
wrmsr(0x10000028, msr);
|
||||
msr.hi = 0x20000000 | membytes>>24;
|
||||
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
|
||||
wrmsr(0x40000029, msr);
|
||||
msr = rdmsr(0x10000028);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
|
||||
msr = rdmsr(0x40000029);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
|
||||
|
||||
/* fixme: SMM MSR 0x10000026 and 0x400000023 */
|
||||
/* calculate the OFFSET field */
|
||||
tmp = membytes - SMM_OFFSET;
|
||||
tmp >>= 12;
|
||||
tmp <<= 8;
|
||||
tmp |= 0x20000000;
|
||||
tmp |= (SMM_OFFSET >> 24);
|
||||
|
||||
/* calculate the PBASE and PMASK fields */
|
||||
tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
|
||||
tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
|
||||
msr.hi = tmp;
|
||||
msr.lo = tmp2;
|
||||
wrmsr(0x10000026, msr);
|
||||
#else
|
||||
msr.hi = 0x2000000f;
|
||||
msr.lo = 0xfbf00100;
|
||||
wrmsr(0x10000028, msr);
|
||||
msr = rdmsr(0x10000028);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
|
||||
wrmsr(0x40000029, msr);
|
||||
msr = rdmsr(0x40000029);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
|
||||
|
||||
msr.hi = 0x2cfbc040;
|
||||
msr.lo = 0x400fffc0;
|
||||
wrmsr(0x10000026, msr);
|
||||
msr = rdmsr(0x10000026);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
|
||||
|
||||
msr.hi = 0x22fffc02;
|
||||
msr.lo = 0x10ffbf00;
|
||||
wrmsr(0x1808, msr);
|
||||
msr = rdmsr(0x1808);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
|
||||
#endif
|
||||
/* now do the default MSR values */
|
||||
|
||||
wrmsr(msr_defaults[0].msr_no, msr);
|
||||
for(i = 0; msr_defaults[i].msr_no; i++) {
|
||||
//msr_t msr;
|
||||
msr.lo = msr_defaults[i].lo;
|
||||
msr.hi = msr_defaults[i].hi;
|
||||
wrmsr(msr_defaults[i].msr_no, msr);
|
||||
//msr = rdmsr(msr_defaults[i].msr_no);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
|
||||
}
|
||||
}
|
||||
|
||||
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
|
||||
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
||||
|
|
@ -264,5 +95,5 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
wrmsr(0x4c00000f, msr);
|
||||
|
||||
/* DRAM working now?? */
|
||||
setup_gx2();
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,13 +29,11 @@ static void southbridge_enable(struct device *dev)
|
|||
msr.lo = sb->lpc_serirq_enable;
|
||||
msr.hi = 0;
|
||||
wrmsr(MDD_LPC_SIRQ, msr);
|
||||
printk_debug("Enabled LPC SERIRQ 0x%x\n", msr.lo);
|
||||
}
|
||||
if (sb->lpc_irq) {
|
||||
msr.lo = sb->lpc_irq;
|
||||
msr.hi = 0;
|
||||
wrmsr(MDD_IRQM_LPC, msr);
|
||||
printk_debug("Enabled lpc irq values 0x%x\n", msr.lo);
|
||||
}
|
||||
|
||||
if (sb->enable_gpio0_inta){
|
||||
|
|
@ -49,7 +47,6 @@ static void southbridge_enable(struct device *dev)
|
|||
/* magic stuff */
|
||||
outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
|
||||
outl(GPIOL_0_SET, GPIO_MAPPER_X);
|
||||
printk_debug("Enabled GPIO0 INTa\n");
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@ static int cs5536_setup_onchipuart(void)
|
|||
* MSR 0x51400014 bit 18:16
|
||||
* 3. Enable UART controller
|
||||
* MSR 0x5140003A bit 0, 1
|
||||
* 4. IRQ routing on IRQ Mapper (before loading OS)
|
||||
* 4. IRQ routing on IRQ Mapper
|
||||
* MSR 0x51400021 bit [27:24]
|
||||
*/
|
||||
msr_t msr;
|
||||
|
|
|
|||
|
|
@ -34,3 +34,4 @@ end
|
|||
|
||||
#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
buildrom ./linuxbios.rom ROM_SIZE "fallback"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue