soc/qualcomm: Link cbmem.c only in romstage
Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36368 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -38,6 +38,7 @@ void setup_dram_mappings(enum dram_state dram)
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/* Map DMA memory */
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/* Map DMA memory */
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mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
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mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
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/* Mark cbmem backing store as ready. */
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/* Mark cbmem backing store as ready. */
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if (ENV_ROMSTAGE)
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ipq_cbmem_backing_store_ready();
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ipq_cbmem_backing_store_ready();
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} else {
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} else {
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mmu_disable_range(DRAM_START, DRAM_SIZE);
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mmu_disable_range(DRAM_START, DRAM_SIZE);
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@ -35,10 +35,9 @@ void setup_dram_mappings(enum dram_state dram)
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mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
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mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
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/* Map DMA memory */
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/* Map DMA memory */
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mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
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mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
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#if ENV_ROMSTAGE
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if (ENV_ROMSTAGE)
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/* Mark cbmem backing store as ready. */
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/* Mark cbmem backing store as ready. */
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ipq_cbmem_backing_store_ready();
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ipq_cbmem_backing_store_ready();
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#endif
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} else {
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} else {
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mmu_disable_range(DRAM_START, DRAM_SIZE);
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mmu_disable_range(DRAM_START, DRAM_SIZE);
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/* Map DMA memory */
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/* Map DMA memory */
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@ -16,7 +16,6 @@
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ifeq ($(CONFIG_SOC_QC_IPQ40XX),y)
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ifeq ($(CONFIG_SOC_QC_IPQ40XX),y)
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bootblock-y += clock.c
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bootblock-y += clock.c
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bootblock-y += cbmem.c
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bootblock-y += gpio.c
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bootblock-y += gpio.c
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bootblock-$(CONFIG_SPI_FLASH) += spi.c
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bootblock-$(CONFIG_SPI_FLASH) += spi.c
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bootblock-y += timer.c
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bootblock-y += timer.c
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@ -43,7 +42,6 @@ romstage-y += blsp.c
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romstage-y += qup.c
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romstage-y += qup.c
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ramstage-y += blobs_init.c
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ramstage-y += blobs_init.c
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ramstage-y += cbmem.c
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ramstage-y += clock.c
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ramstage-y += clock.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += lcc.c
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ramstage-y += lcc.c
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@ -31,7 +31,7 @@ void *cbmem_top_chipset(void)
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* with components that utilize cbmem in romstage (e.g. vboot_locator
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* with components that utilize cbmem in romstage (e.g. vboot_locator
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* for loading ipq blobs before DRAM is initialized).
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* for loading ipq blobs before DRAM is initialized).
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*/
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*/
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if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0))
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if (cbmem_backing_store_ready == 0)
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return NULL;
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return NULL;
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return _memlayout_cbmem_top;
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return _memlayout_cbmem_top;
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@ -42,7 +42,6 @@ romstage-y += gsbi.c
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romstage-y += qup.c
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romstage-y += qup.c
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ramstage-y += blobs_init.c
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ramstage-y += blobs_init.c
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ramstage-y += cbmem.c
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ramstage-y += clock.c
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ramstage-y += clock.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += lcc.c
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ramstage-y += lcc.c
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@ -32,7 +32,7 @@ void *cbmem_top_chipset(void)
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* (e.g. vboot_locator for loading ipq blobs before DRAM is
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* (e.g. vboot_locator for loading ipq blobs before DRAM is
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* initialized).
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* initialized).
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*/
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*/
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if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0))
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if (cbmem_backing_store_ready == 0)
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return NULL;
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return NULL;
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return _memlayout_cbmem_top;
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return _memlayout_cbmem_top;
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