soc/qualcomm: Link cbmem.c only in romstage

Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36368
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/gale/mmu.c

@@ -38,7 +38,8 @@ void setup_dram_mappings(enum dram_state dram)
 		/* Map DMA memory */
 		mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
 		/* Mark cbmem backing store as ready. */
-		ipq_cbmem_backing_store_ready();
+		if (ENV_ROMSTAGE)
+			ipq_cbmem_backing_store_ready();
 	} else {
 		mmu_disable_range(DRAM_START, DRAM_SIZE);
 		/* Map DMA memory */

src/mainboard/google/storm/mmu.c

@@ -35,10 +35,9 @@ void setup_dram_mappings(enum dram_state dram)
 		mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
 		/* Map DMA memory */
 		mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
-#if ENV_ROMSTAGE
-		/* Mark cbmem backing store as ready. */
-		ipq_cbmem_backing_store_ready();
-#endif
+		if (ENV_ROMSTAGE)
+			/* Mark cbmem backing store as ready. */
+			ipq_cbmem_backing_store_ready();
 	} else {
 		mmu_disable_range(DRAM_START, DRAM_SIZE);
 		/* Map DMA memory */

src/soc/qualcomm/ipq40xx/Makefile.inc

@@ -16,7 +16,6 @@
 ifeq ($(CONFIG_SOC_QC_IPQ40XX),y)
 
 bootblock-y += clock.c
-bootblock-y += cbmem.c
 bootblock-y += gpio.c
 bootblock-$(CONFIG_SPI_FLASH) += spi.c
 bootblock-y += timer.c
@@ -43,7 +42,6 @@ romstage-y += blsp.c
 romstage-y += qup.c
 
 ramstage-y += blobs_init.c
-ramstage-y += cbmem.c
 ramstage-y += clock.c
 ramstage-y += gpio.c
 ramstage-y += lcc.c

src/soc/qualcomm/ipq40xx/cbmem.c

@@ -31,7 +31,7 @@ void *cbmem_top_chipset(void)
 	 * with components that utilize cbmem in romstage (e.g. vboot_locator
 	 * for loading ipq blobs before DRAM is initialized).
 	 */
-	if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0))
+	if (cbmem_backing_store_ready == 0)
 		return NULL;
 
 	return _memlayout_cbmem_top;

src/soc/qualcomm/ipq806x/Makefile.inc

@@ -42,7 +42,6 @@ romstage-y += gsbi.c
 romstage-y += qup.c
 
 ramstage-y += blobs_init.c
-ramstage-y += cbmem.c
 ramstage-y += clock.c
 ramstage-y += gpio.c
 ramstage-y += lcc.c

src/soc/qualcomm/ipq806x/cbmem.c

@@ -32,7 +32,7 @@ void *cbmem_top_chipset(void)
 	 * (e.g. vboot_locator for loading ipq blobs before DRAM is
 	 * initialized).
 	 */
-	if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0))
+	if (cbmem_backing_store_ready == 0)
 		return NULL;
 
 	return _memlayout_cbmem_top;