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mb/google/hatch/variants/kohaku: Add support for LPDDR3 configurations 

First configuration supported is 8 GB system memory:
4 x 2 GB (K4E6E304ED-EGCG).

BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ibd92d585118ff75492e8a7188dcdb2a286836d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Paul Fagerburg 2019-04-18 16:52:06 -06:00 committed by Furquan Shaikh
parent cb42f4d467
commit d3d41b348d
3 changed files with 120 additions and 6 deletions
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32
src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex Normal file
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9
src/mainboard/google/hatch/variants/kohaku/Makefile.inc
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## GNU General Public License for more details.
##
SPD_SOURCES = 4G_2400 # 0b000
SPD_SOURCES += empty_ddr4 # 0b001
SPD_SOURCES += 8G_2400 # 0b010
SPD_SOURCES += 8G_2666 # 0b011
SPD_SOURCES += 16G_2400 # 0b100
SPD_SOURCES += 16G_2666 # 0b101
SPD_SOURCES = LP_8G_2133 # 0b000
romstage-y += memory.c
bootblock-y += gpio.c
ramstage-y += gpio.c

85
src/mainboard/google/hatch/variants/kohaku/memory.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
#include <soc/cnl_memcfg_init.h>
#include <string.h>
static const struct cnl_mb_cfg baseboard_memcfg = {
/*
* The dqs_map arrays map the SoC pins to the lpddr3 pins
* for both channels.
*
* "The index of the array is CPU byte number, the values are DRAM byte
* numbers." - doc #573387
*
* the index = pin number on SoC
* the value = pin number on lpddr3 part
*/
.dqs_map[DDR_CH0] = { 0, 1, 3, 2, 5, 7, 6, 4 },
.dqs_map[DDR_CH1] = { 1, 3, 2, 0, 5, 7, 6, 4 },
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0x0, 0xf0},
{0xf, 0xf0},
{0xf, 0x0},
{0xff, 0x0},
{0xff, 0x0}
},
.dq_map[DDR_CH1] = {
{0xf, 0xf0},
{0x0, 0xf0},
{0xf, 0xf0},
{0xf, 0x0},
{0xff, 0x0},
{0xff, 0x0}
},
/* Kohaku uses 200, 80.6 and 162 rcomp resistors */
.rcomp_resistor = { 200, 81, 162 },
/* Kohaku Rcomp target values */
.rcomp_targets = { 100, 40, 40, 23, 40 },
/* Set CaVref config to 0 for LPDDR3 */
.vref_ca_config = 0,
/* Disable Early Command Training */
.ect = 0,
};
void variant_memory_params(struct cnl_mb_cfg *bcfg)
{
memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
/*
* GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
* channel skus and 0 for dual channel skus.
*/
if (gpio_get(GPP_F2) == 1) {
/*
* Single channel config: for kohaku, Channel 0 is
* always populated.
*/
bcfg->channel_empty[0] = 0;
bcfg->channel_empty[1] = 1;
} else {
/* Dual channel config: both channels populated. */
bcfg->channel_empty[0] = 0;
bcfg->channel_empty[1] = 0;
}
}