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soc/mediatek/common: Add DPM_FOUR_CHANNEL option 

Add DPM_FOUR_CHANNEL option for 4 channel configuration for DPM.
Publicize reset_dpm() as dpm_reset() for external reference.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If6e0d5c4d16a7ddd69c4a427488f8899870db327
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Ryan Chuang 2021-06-18 19:47:39 +08:00 committed by Hung-Te Lin
parent aff42bc6a4
commit d41a5ae489
3 changed files with 39 additions and 14 deletions
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6
src/soc/mediatek/common/Kconfig
View File

@ -34,4 +34,10 @@ config CLEAR_WDT_MODE_REG
help
Enable this option to clear WTD mode register explicitly.
config DPM_FOUR_CHANNEL
bool
default n
help
This option enables four channel configuration for DPM.
endif

33
src/soc/mediatek/common/dpm.c
View File

@ -5,16 +5,6 @@
#include <soc/mcu_common.h>
#include <soc/symbols.h>
static void reset_dpm(struct mtk_mcu *mcu)
{
/* write bootargs */
write32(&mtk_dpm->twam_window_len, 0x0);
write32(&mtk_dpm->twam_mon_type, 0x0);
/* free RST */
setbits32(&mtk_dpm->sw_rstn, DPM_SW_RSTN_RESET);
}
static struct mtk_mcu dpm_mcu[] = {
{
.firmware_name = CONFIG_DPM_DM_FIRMWARE,
@ -23,15 +13,32 @@ static struct mtk_mcu dpm_mcu[] = {
{
.firmware_name = CONFIG_DPM_PM_FIRMWARE,
.run_address = (void *)DPM_PM_SRAM_BASE,
.reset = reset_dpm,
.priv = mtk_dpm,
.reset = dpm_reset,
},
};
void dpm_reset(struct mtk_mcu *mcu)
{
struct dpm_regs *dpm = mcu->priv;
/* write bootargs */
write32(&dpm->twam_window_len, 0x0);
write32(&dpm->twam_mon_type, 0x0);
/* free RST */
setbits32(&dpm->sw_rstn, DPM_SW_RSTN_RESET);
}
int dpm_init(void)
{
int i;
struct mtk_mcu *dpm;
if (CONFIG(DPM_FOUR_CHANNEL))
if (dpm_4ch_init())
return -1;
/* config DPM SRAM layout */
clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1);
@ -43,5 +50,9 @@ int dpm_init(void)
return -1;
}
if (CONFIG(DPM_FOUR_CHANNEL))
if (dpm_4ch_para_setting())
return -1;
return 0;
}

14
src/soc/mediatek/common/include/soc/dpm.h
View File

@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_DPM_H__
#define __SOC_MEDIATEK_DPM_H__
#ifndef __SOC_MEDIATEK_COMMON_DPM_H__
#define __SOC_MEDIATEK_COMMON_DPM_H__
#include <soc/addressmap.h>
#include <soc/mcu_common.h>
#include <stdint.h>
#include <types.h>
@ -41,9 +42,16 @@ check_member(dpm_regs, status_4, 0x70B0);
#define DPM_MEM_RATIO_OFFSET 28
#define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET)
#define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET)
#define DRAMC_MCU_SRAM_ISOINT_B_LSB BIT(1)
#define DRAMC_MCU2_SRAM_ISOINT_B_LSB BIT(1)
#define DRAMC_MCU_SRAM_SLEEP_B_LSB BIT(4)
#define DRAMC_MCU2_SRAM_SLEEP_B_LSB BIT(4)
static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE;
void dpm_reset(struct mtk_mcu *mcu);
int dpm_init(void);
int dpm_4ch_para_setting(void);
int dpm_4ch_init(void);
#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */
#endif /* __SOC_MEDIATEK_COMMON_DPM_H__ */