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AGESA: Avoid cpuRegisters.h include 

Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-09-24 16:23:57 +03:00
parent d229d4a28e
commit d41feed800
9 changed files with 7 additions and 16 deletions
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3
src/northbridge/amd/agesa/family15/northbridge.c
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@ -35,7 +35,6 @@
#include <AGESA.h> #include <AGESA.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -931,7 +930,7 @@ static void cpu_bus_scan(device_t dev)
#endif #endif
/* Get Max Number of cores(MNC) */ /* Get Max Number of cores(MNC) */
coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);

3
src/northbridge/amd/agesa/family15tn/northbridge.c
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@ -36,7 +36,6 @@
#include <Porting.h> #include <Porting.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -921,7 +920,7 @@ static void cpu_bus_scan(device_t dev)
#endif #endif
/* Get Max Number of cores(MNC) */ /* Get Max Number of cores(MNC) */
coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);

3
src/northbridge/amd/agesa/family16kb/northbridge.c
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@ -35,7 +35,6 @@
#include <AGESA.h> #include <AGESA.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -937,7 +936,7 @@ static void cpu_bus_scan(device_t dev)
#endif #endif
/* Get Max Number of cores(MNC) */ /* Get Max Number of cores(MNC) */
coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);

3
src/northbridge/amd/pi/00630F01/northbridge.c
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@ -32,7 +32,6 @@
#include <FieldAccessors.h> #include <FieldAccessors.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
@ -935,7 +934,7 @@ static void cpu_bus_scan(device_t dev)
#endif #endif
/* Get Max Number of cores(MNC) */ /* Get Max Number of cores(MNC) */
coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);

3
src/northbridge/amd/pi/00660F01/northbridge.c
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@ -32,7 +32,6 @@
#include <FieldAccessors.h> #include <FieldAccessors.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
@ -934,7 +933,7 @@ static void cpu_bus_scan(device_t dev)
#endif #endif
/* Get Max Number of cores(MNC) */ /* Get Max Number of cores(MNC) */
coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);

3
src/northbridge/amd/pi/00730F01/northbridge.c
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@ -32,7 +32,6 @@
#include <FieldAccessors.h> #include <FieldAccessors.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
@ -960,7 +959,7 @@ static void cpu_bus_scan(device_t dev)
#endif #endif
/* Get Max Number of cores(MNC) */ /* Get Max Number of cores(MNC) */
coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);

1
src/northbridge/amd/pi/agesawrapper.c
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@ -18,7 +18,6 @@
#include <cbmem.h> #include <cbmem.h>
#include <delay.h> #include <delay.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpuRegisters.h>
#include <FchPlatform.h> #include <FchPlatform.h>
#include <heapManager.h> #include <heapManager.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>

1
src/soc/amd/common/agesawrapper.c
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@ -18,7 +18,6 @@
#include <cbmem.h> #include <cbmem.h>
#include <delay.h> #include <delay.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpuRegisters.h>
#include <FchPlatform.h> #include <FchPlatform.h>
#include <heapManager.h> #include <heapManager.h>
#include <agesawrapper.h> #include <agesawrapper.h>

3
src/soc/amd/stoneyridge/northbridge.c
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@ -40,7 +40,6 @@
* and not set by vendorcode * and not set by vendorcode
*/ */
#include <AGESA.h> #include <AGESA.h>
#include <cpuRegisters.h>
#include <FieldAccessors.h> #include <FieldAccessors.h>
#include <Options.h> #include <Options.h>
#include <Porting.h> #include <Porting.h>
@ -573,7 +572,7 @@ void cpu_bus_scan(device_t dev)
} }
/* Get max and actual number of cores */ /* Get max and actual number of cores */
pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT); pccount = cpuid_ecx(0x80000008);
core_max = 1 << ((pccount >> 12) & 0xf); core_max = 1 << ((pccount >> 12) & 0xf);
core_nums = (pccount & 0xF); core_nums = (pccount & 0xF);