i5000: Fix resource allocation

The current code didn't reserve static resource the right way.
Also reduce TOLM to 0xd0000000, because those boards have so many PCI
devices that 0xe0000000 isn't sufficient.

Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1220
Tested-by: build bot (Jenkins)

src/northbridge/intel/i5000/northbridge.c

@@ -31,6 +31,9 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include "chip.h"
+#if CONFIG_WRITE_HIGH_TABLES
+#include <cbmem.h>
+#endif
 
 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
@@ -43,60 +46,18 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
-static struct pci_operations intel_pci_ops = {
+static void mc_read_resources(device_t dev)
-	.set_subsystem    = intel_set_subsystem,
-};
-
-static struct device_operations mc_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.scan_bus         = 0,
-	.ops_pci          = &intel_pci_ops,
-};
-
-static const unsigned short nb_ids[] = {
-	0x25c0,	/* 5000X */
-	0x25d0, /* 5000Z */
-	0x25d4, /* 5000V */
-	0x25d8, /* 5000P */
-	0};
-
-static const struct pci_driver mc_driver __pci_driver = {
-	.ops    = &mc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.devices = nb_ids,
-};
-
-static void cpu_bus_init(device_t dev)
-{
-	initialize_cpus(dev->link_list);
-}
-
-static void cpu_bus_noop(device_t dev)
-{
-}
-static struct device_operations cpu_bus_ops = {
-	.read_resources   = cpu_bus_noop,
-	.set_resources    = cpu_bus_noop,
-	.enable_resources = cpu_bus_noop,
-	.init             = cpu_bus_init,
-	.scan_bus         = 0,
-};
-
-#if CONFIG_WRITE_HIGH_TABLES
-#include <cbmem.h>
-#endif
-
-static void pci_domain_set_resources(device_t dev)
 {
 	struct resource *resource;
 	uint32_t hecbase, amsize, tolm;
 	uint64_t ambase, memsize;
 	int idx = 0;
+
 	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
 	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
 
+	pci_dev_read_resources(dev);
+
 	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
 	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
 	hecbase &= 0xffff;
@@ -119,8 +80,8 @@ static void pci_domain_set_resources(device_t dev)
 
 	memsize <<= 24;
 	printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
-	if (memsize > 0xe0000000) {
+	if (memsize > 0xd0000000) {
-		memsize -= 0xe0000000;
+		memsize -= 0xd0000000;
 		printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
 		ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
 	}
@@ -156,8 +117,6 @@ static void pci_domain_set_resources(device_t dev)
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
-	assign_resources(dev->link_list);
-
 #if CONFIG_WRITE_HIGH_TABLES
 	/* Leave some space for ACPI, PIRQ and MP tables */
 	high_tables_base = tolm - HIGH_MEMORY_SIZE;
@@ -166,6 +125,51 @@ static void pci_domain_set_resources(device_t dev)
 #endif
 }
 
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = mc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const unsigned short nb_ids[] = {
+	0x25c0,	/* 5000X */
+	0x25d0, /* 5000Z */
+	0x25d4, /* 5000V */
+	0x25d8, /* 5000P */
+	0};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.devices = nb_ids,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+static void pci_domain_set_resources(device_t dev)
+{
+	assign_resources(dev->link_list);
+}
+
 static struct device_operations pci_domain_ops = {
 	.read_resources   = pci_domain_read_resources,
 	.set_resources    = pci_domain_set_resources,

src/northbridge/intel/i5000/raminit.c

@@ -1349,8 +1349,8 @@ static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
 
 	i5000_setup_interleave(setup);
 
-	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+	if ((tolm = MIN(setup->totalmem, 0xd00)) > 0xd00)
-		tolm = 0xe00;
+		tolm = 0xd00;
 
 	tolm <<= 4;
 	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
@@ -1759,7 +1759,7 @@ void i5000_fbdimm_init(void)
 
 #if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
 	if (ram_check_nodie(0x000000, 0x0a0000) ||
-	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) {
 		i5000_try_restart("RAM verification failed");
 
 	}