coreboot rush: Add support for basic romstage

Add basic romstage support for rush. Since, dram init needs to be done before we
can jump to armv8 core, romstage will run on armv4 core as well. Thus,
correcting the compiler selection options.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Prints romstage banner and initial printk

Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205763
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a
Reviewed-on: http://review.coreboot.org/8573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/arch/arm/armv4/Makefile.inc

@@ -49,6 +49,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV4),y)
 
 romstage-c-ccopts += $(armv4_flags)
 romstage-S-ccopts += $(armv4_flags)
+romstage-y += cache.c
 
 endif # CONFIG_ARCH_ROMSTAGE_ARMV4
 

src/mainboard/google/rush/romstage.c

@@ -20,11 +20,19 @@
 #include <arch/stages.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <arch/exception.h>
 
 void main(void)
 {
 	void *entry;
 
+	console_init();
+	exception_init();
+
+	printk(BIOS_INFO, "T132: romstage here\n");
+
+	while (1);
+
         entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
         stage_exit(entry);
 }

src/soc/nvidia/tegra132/Kconfig

@@ -3,13 +3,14 @@ config SOC_NVIDIA_TEGRA132
 	default n
 	select ARCH_BOOTBLOCK_ARMV4
 	select ARCH_VERSTAGE_ARMV4
-	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV4
 	select ARCH_RAMSTAGE_ARMV8_64
 	select ARM_LPAE
 	select DYNAMIC_CBMEM
 	select BOOTBLOCK_CONSOLE
 	select HAVE_UART_SPECIAL
 	select HAVE_UART_MEMORY_MAPPED
+	select EARLY_CONSOLE
 	select ARM_BOOTBLOCK_CUSTOM
 
 if SOC_NVIDIA_TEGRA132