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mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5 

Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage.

BUG=None
BRANCH=poppy
TEST=Verified the leakage is gone after update coreboot

Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Seunghwan Kim 2018-06-15 13:30:42 +09:00 committed by Furquan Shaikh
parent e5a9e60fc5
commit d4475fc6f9
2 changed files with 30 additions and 0 deletions
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2
src/mainboard/google/poppy/variants/nautilus/Makefile.inc
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@ -10,3 +10,5 @@ romstage-y += memory.c
ramstage-y += gpio.c
ramstage-y += nhlt.c
ramstage-y += mainboard.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

28
src/mainboard/google/poppy/variants/nautilus/smihandler.c Normal file
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@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <baseboard/variants.h>
#include <gpio.h>
#define LTE3_PWROFF_L GPP_D0
void variant_smi_sleep(u8 slp_typ)
{
if (slp_typ == ACPI_S5) {
/* Turn off LTE module */
gpio_set(LTE3_PWROFF_L, 0);
}
}