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Added CL7 support 

according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf"
Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)
page 16 and page 60, CL7 support added

Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/14976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2016-05-26 19:53:29 +02:00 committed by Stefan Reinauer
parent 579fdb4910
commit d450609145
2 changed files with 2 additions and 0 deletions
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1
src/include/spd.h
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@ -145,6 +145,7 @@ enum spd_memory_type {
#define SPD_CAS_LATENCY_DDR2_4 (1 << 4)
#define SPD_CAS_LATENCY_DDR2_5 (1 << 5)
#define SPD_CAS_LATENCY_DDR2_6 (1 << 6)
#define SPD_CAS_LATENCY_DDR2_7 (1 << 7)
/* SPD_SUPPORTED_BURST_LENGTHS values. */
#define SPD_BURST_LENGTH_1 1

1
src/include/spd_ddr2.h
View File

@ -80,6 +80,7 @@
#define SPD_CAS_LAT_4 (1<<4)
#define SPD_CAS_LAT_5 (1<<5)
#define SPD_CAS_LAT_6 (1<<6)
#define SPD_CAS_LAT_7 (1<<7)
#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */
#define SPD_TRRD 28