{soc,vc,mb}/intel: Drop support for Cannon Lake SoC
Drop the support for the Intel Cannon Lake SoC for various reasons: * Most people can't use coreboot on Cannon Lake, since the required FSP binaries aren't publicly available. Given that FSP binaries for several newer platforms have been released, it's very unlikely that Cannon Lake FSP will ever be released. * It seems there is no interest in this, since the reference mainboard is the only available mainboard in tree. Also, remove the related reference mainboard intel/cannonlake_rvp and its FSP headers in intel/fsp2_0/cannonlake. Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
Patrick Georgi
parent
5569bddf66
commit
d456f65056
36 changed files with 0 additions and 8033 deletions
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@ -1,70 +0,0 @@
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if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select HAVE_SPD_IN_CBFS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select HAVE_SPD_IN_CBFS
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_DA7219
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select DRIVERS_I2C_MAX98373
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select DRIVERS_GENERIC_MAX98357A
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select SOC_INTEL_CANNONLAKE
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select MAINBOARD_USES_IFD_EC_REGION
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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config MAINBOARD_DIR
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string
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default "intel/cannonlake_rvp"
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config VARIANT_DIR
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string
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default "cnl_u" if BOARD_INTEL_CANNONLAKE_RVPU
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default "cnl_y" if BOARD_INTEL_CANNONLAKE_RVPY
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config MAINBOARD_PART_NUMBER
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string
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default "Cannonlake RVP"
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config MAINBOARD_FAMILY
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string
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default "Intel_cannonlake_rvp"
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config MAX_CPUS
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int
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default 8
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config DEVICETREE
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config INCLUDE_SND_MAX98357_DA7219_NHLT
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bool "Include blobs for audio with MAX98357_DA7219"
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select NHLT_DMIC_4CH_16B
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select NHLT_DMIC_2CH_16B
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select NHLT_DA7219
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select NHLT_MAX98357
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config INCLUDE_SND_MAX98373_NHLT
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bool "Include blobs for audio with MAX98373"
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select NHLT_DMIC_4CH_16B
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select NHLT_DMIC_2CH_16B
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select NHLT_MAX98373
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config DIMM_SPD_SIZE
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int
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default 512
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA
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config UART_FOR_CONSOLE
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int
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default 2
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endif
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@ -1,4 +0,0 @@
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config BOARD_INTEL_CANNONLAKE_RVPU
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bool "Cannonlake U LPDDR4 RVP"
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config BOARD_INTEL_CANNONLAKE_RVPY
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bool "Cannonlake Y LPDDR4 RVP"
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@ -1,21 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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subdirs-y += spd
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage_fsp_params.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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smm-y += smihandler.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -1,6 +0,0 @@
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Vendor name: Intel
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Board name: Cannonlake rvp
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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@ -1,45 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <baseboard/variants.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_lid_switch(void)
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{
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/* Lid always open */
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return 1;
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}
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int get_recovery_mode_switch(void)
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{
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return 0;
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}
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int get_write_protect_state(void)
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{
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/* No write protect */
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return 0;
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *gpios;
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size_t num;
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gpios = variant_cros_gpios(&num);
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chromeos_acpi_gpio_generate(gpios, num);
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}
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@ -1,45 +0,0 @@
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FLASH@0xff000000 0x1000000 {
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SI_ALL@0x0 0x380000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x01000 0x80000
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SI_ME@0x81000 0x2ff000
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}
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SI_BIOS@0x380000 0xc80000 {
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RW_SECTION_A@0x0 0x368000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x357fc0
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RW_FWID_A@0x367fc0 0x40
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}
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RW_SECTION_B@0x368000 0x368000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x357fc0
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RW_FWID_B@0x367fc0 0x40
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}
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RW_MISC@0x6d0000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG(PRESERVE)@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x28000 0x2000
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RW_NVRAM(PRESERVE)@0x2a000 0x6000
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}
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SMMSTORE(PRESERVE)@0x700000 0x40000
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RW_LEGACY(CBFS)@0x740000 0x1c0000
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WP_RO@0x900000 0x380000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x370000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x280000
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}
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}
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}
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}
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@ -1,33 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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}
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#if CONFIG(CHROMEOS)
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// Chrome OS specific
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -1,55 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <nhlt.h>
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#include <soc/gpio.h>
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#include <soc/nhlt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <variant/gpio.h>
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static void mainboard_init(void *chip_info)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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static unsigned long mainboard_write_acpi_tables(const struct device *device,
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unsigned long current,
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acpi_rsdp_t *rsdp)
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{
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uintptr_t start_addr;
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uintptr_t end_addr;
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struct nhlt *nhlt;
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start_addr = current;
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nhlt = nhlt_init();
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if (nhlt == NULL)
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return start_addr;
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variant_nhlt_init(nhlt);
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end_addr = nhlt_soc_serialize(nhlt, start_addr);
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if (end_addr != start_addr)
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acpi_add_table(rsdp, (void *)start_addr);
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return end_addr;
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
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dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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@ -1,37 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <fsp/api.h>
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#include <soc/romstage.h>
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#include "spd/spd.h"
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#include <spd_bin.h>
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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FSP_M_CONFIG *mem_cfg;
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mem_cfg = &mupd->FspmConfig;
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u8 spd_index;
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mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
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mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
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mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);
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mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);
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mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
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mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
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mem_cfg->DqPinsInterleaved = 0;
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mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
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mem_cfg->ECT = 1; /* Early Command Training Enabled */
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spd_index = 2;
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struct region_device spd_rdev;
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if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
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die("spd.bin not found\n");
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mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
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/* Memory leak is ok since we have memory mapped boot media */
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mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
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mem_cfg->RefClk = 0; /* Auto Select CLK freq */
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mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
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}
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@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <intelblocks/smihandler.h>
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#include <soc/nvs.h>
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int mainboard_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x99:
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printk(BIOS_DEBUG, "Sample\n");
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gnvs->smif = 0;
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break;
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default:
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return 0;
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}
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/* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*
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* For now, we force the return value to 0 and log all traps to
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* see what's going on.
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*/
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return 1;
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}
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@ -1,12 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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romstage-y += spd_util.c
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SPD_SOURCES = empty # 0b000
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SPD_SOURCES += samsung_ddr4_4GB # 0b001 Dual Channel 4GB
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SPD_SOURCES += samsung_lpddr4_8GB # 0b001 Dual Channel 8GB
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SPD_SOURCES += empty # 0b011
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SPD_SOURCES += empty # 0b100
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SPD_SOURCES += empty # 0b101
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SPD_SOURCES += empty # 0b110
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SPD_SOURCES += empty # 0b111
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@ -1,32 +0,0 @@
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00
|
||||
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08
|
||||
00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
|
||||
16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20
|
||||
0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31
|
||||
34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE
|
||||
00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00
|
||||
01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00
|
||||
48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
|
||||
02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
|
||||
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
void mainboard_fill_dq_map_ch0(void *dq_map_ptr);
|
||||
void mainboard_fill_dq_map_ch1(void *dq_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);
|
||||
void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
|
||||
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
|
||||
#endif
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "spd.h"
|
||||
|
||||
void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
|
||||
{
|
||||
/* DQ byte map Ch0 */
|
||||
const u8 dq_map[12] = {
|
||||
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
|
||||
}
|
||||
|
||||
void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
|
||||
{
|
||||
const u8 dq_map[12] = {
|
||||
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
|
||||
}
|
||||
|
||||
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
|
||||
{
|
||||
/* DQS CPU<>DRAM map Ch0 */
|
||||
const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
|
||||
|
||||
const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
|
||||
|
||||
if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU))
|
||||
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
|
||||
else
|
||||
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
|
||||
}
|
||||
|
||||
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
|
||||
{
|
||||
/* DQS CPU<>DRAM map Ch1 */
|
||||
const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
|
||||
|
||||
const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
|
||||
|
||||
if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU))
|
||||
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
|
||||
else
|
||||
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
|
||||
}
|
||||
|
||||
void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
|
||||
{
|
||||
/* Rcomp resistor */
|
||||
const u16 RcompResistor[3] = { 100, 100, 100 };
|
||||
memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
|
||||
}
|
||||
|
||||
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
|
||||
{
|
||||
/* Rcomp target */
|
||||
static const u16 RcompTarget[5] = { 80, 40, 40, 40, 30 };
|
||||
|
||||
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
|
||||
}
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
bootblock-y += gpio.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += nhlt.c
|
||||
|
|
@ -1,306 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/* Pad configuration in ramstage*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* GPPC */
|
||||
/* A0 : RCINB_TIME_SYNC_1 */
|
||||
/* A1 : ESPI_IO_0 */
|
||||
/* A2 : ESPI_IO_1 */
|
||||
/* A3 : ESPI_IO_2 */
|
||||
/* A4 : ESPI_IO_3 */
|
||||
/* A5 : ESPI_CSB */
|
||||
/* A6 : SERIRQ */
|
||||
/* A7 : PRIQAB_GSP10_CS1B */
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE),
|
||||
/* A8 : CLKRUNB */
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
/* A9 : CLKOUT_LPC_0_ESPI_CLK */
|
||||
/* A10 : CLKOUT_LPC_1 */
|
||||
/* A11 : PMEB_GSP11_CS1B */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL),
|
||||
/* A12 : BM_BUSYB_ISH__GP_6 */
|
||||
/* A13 : SUSWARNB_SUSPWRDNACK */
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
/* A14 : SUS_STATB_ESPI_RESETB */
|
||||
/* A15 : SUSACKB */
|
||||
PAD_CFG_GPO(GPP_A15, 1, PLTRST),
|
||||
/* A16 : SD_1P8_SEL */
|
||||
PAD_CFG_GPO(GPP_A16, 0, PLTRST),
|
||||
/* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */
|
||||
/* A18 : ISH_GP_0 */
|
||||
PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),
|
||||
/* A19 : ISH_GP_1 */
|
||||
PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),
|
||||
/* A20 : aduio codec irq */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),
|
||||
/* A21 : ISH_GP_3 */
|
||||
PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),
|
||||
/* A22 : ISH_GP_4 */
|
||||
PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1),
|
||||
/* A23 : ISH_GP_5 */
|
||||
PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
|
||||
|
||||
/* B0 : CORE_VID_0 */
|
||||
/* B1 : CORE_VID_1 */
|
||||
/* B2 : VRALERTB */
|
||||
PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE),
|
||||
/* B3 : CPU_GP_2 */
|
||||
PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE),
|
||||
/* B4 : CPU_GP_3 */
|
||||
PAD_CFG_GPO(GPP_B4, 1, DEEP),
|
||||
/* B5 : SRCCLKREQB_0 */
|
||||
/* B6 : SRCCLKREQB_1 */
|
||||
/* B7 : SRCCLKREQB_2 */
|
||||
/* B8 : SRCCLKREQB_3 */
|
||||
/* B9 : SRCCLKREQB_4 */
|
||||
/* B10 : SRCCLKREQB_5 */
|
||||
/* B11 : EXT_PWR_GATEB */
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
/* B12 : SLP_S0B */
|
||||
/* B13 : PLTRSTB */
|
||||
/* B14 : SPKR */
|
||||
PAD_CFG_GPO(GPP_B14, 1, PLTRST),
|
||||
/* B15 : GSPI0_CS0B */
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
/* B16 : GSPI0_CLK */
|
||||
PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),
|
||||
/* B17 : GSPI0_MISO */
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
/* B18 : GSPI0_MOSI */
|
||||
PAD_CFG_GPO(GPP_B18, 1, PLTRST),
|
||||
/* B19 : GSPI1_CS0B */
|
||||
/* B20 : GSPI1_CLK_NFC_CLK */
|
||||
/* B21 : GSPI1_MISO_NFC_CLKREQ */
|
||||
/* B22 : GSP1_MOSI */
|
||||
/* B23 : SML1ALERTB_PCHHOTB */
|
||||
PAD_CFG_GPO(GPP_B23, 1, DEEP),
|
||||
|
||||
/* C0 : SMBCLK */
|
||||
/* C1 : SMBDATA */
|
||||
/* C2 : SMBALERTB */
|
||||
PAD_CFG_GPO(GPP_C2, 1, DEEP),
|
||||
/* C3 : SML0CLK */
|
||||
/* C4 : SML0DATA */
|
||||
/* C5 : SML0ALERTB */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),
|
||||
/* C6 : SML1CLK */
|
||||
/* C7 : SML1DATA */
|
||||
/* C8 : UART0_RXD */
|
||||
PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT),
|
||||
/* C9 : UART0_TXD */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE),
|
||||
/* C10 : UART0_RTSB */
|
||||
PAD_CFG_GPO(GPP_C10, 0, PLTRST),
|
||||
/* C11 : UART0_CTSB */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL),
|
||||
/* C12 : UART1_RXD_ISH_UART1_RXD */
|
||||
PAD_CFG_GPO(GPP_C12, 1, PLTRST),
|
||||
/* C13 : UART1_RXD_ISH_UART1_TXD */
|
||||
/* C14 : UART1_RXD_ISH_UART1_RTSB */
|
||||
/* C15 : UART1_RXD_ISH_UART1_CTSB */
|
||||
PAD_CFG_GPO(GPP_C15, 1, PLTRST),
|
||||
/* C16 : I2C0_SDA */
|
||||
/* C17 : I2C0_SCL */
|
||||
/* C18 : I2C1_SDA */
|
||||
/* C19 : I2C1_SCL */
|
||||
/* C20 : UART2_RXD */
|
||||
/* C21 : UART2_TXD */
|
||||
/* C22 : UART2_RTSB */
|
||||
/* C23 : UART2_CTSB */
|
||||
|
||||
/* D0 : SPI1_CSB_BK_0 */
|
||||
/* D1 : SPI1_CLK_BK_1 */
|
||||
/* D2 : SPI1_MISO_IO_1_BK_2 */
|
||||
/* D3 : SPI1_MOSI_IO_0_BK_3 */
|
||||
/* D4 : IMGCLKOUT_0_BK_4 */
|
||||
/* D5 : ISH_I2C0_SDA */
|
||||
/* D6 : ISH_I2C0_SCL */
|
||||
/* D7 : ISH_I2C1_SDA */
|
||||
/* D8 : ISH_I2C1_SCL */
|
||||
/* D9 : ISH_SPI_CSB */
|
||||
PAD_CFG_GPO(GPP_D9, 1, PLTRST),
|
||||
/* D10 : ISH_SPI_CLK */
|
||||
PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE),
|
||||
/* D11 : ISH_SPI_MISO_GP_BSSB_CLK */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),
|
||||
/* D12 : ISH_SPI_MOSI_GP_BSSB_DI */
|
||||
/* D13 : ISH_UART0_RXD_SML0BDATA */
|
||||
PAD_CFG_GPO(GPP_D13, 1, DEEP),
|
||||
/* D14 : ISH_UART0_TXD_SML0BCLK */
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
/* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */
|
||||
/* D16 : ISH_UART0_CTSB_SML0BALERTB */
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),
|
||||
/* D17 : DMIC_CLK_1_SNDW3_CLK */
|
||||
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
|
||||
/* D18 : DMIC_DATA_1_SNDW3_DATA */
|
||||
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
|
||||
/* D19 : DMIC_CLK_0_SNDW4_CLK */
|
||||
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
|
||||
/* D20 : DMIC_DATA_0_SNDW4_DATA */
|
||||
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
|
||||
/* D21 : SPI1_IO_2 */
|
||||
PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),
|
||||
/* D22 : SPI1_IO_3 */
|
||||
PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),
|
||||
/* D23 : SPP_MCLK */
|
||||
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
/* E0 : SATAXPCIE_0_SATAGP_0 */
|
||||
#if CONFIG(BOARD_INTEL_CANNONLAKE_RVPY)
|
||||
PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
|
||||
#endif
|
||||
/* E1 : SATAXPCIE_1_SATAGP_1 */
|
||||
/* E2 : SATAXPCIE_2_SATAGP_2 */
|
||||
PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),
|
||||
/* E3 : CPU_GP_0 */
|
||||
PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
|
||||
/* E4 : SATA_DEVSLP_0 */
|
||||
PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
|
||||
/* E5 : SATA_DEVSLP_1 */
|
||||
/* E6 : SATA_DEVSLP_2 */
|
||||
PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),
|
||||
/* E7 : CPU_GP_1 */
|
||||
PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),
|
||||
/* E8 : SATA_LEDB */
|
||||
/* E9 : USB2_OCB_0_GP_BSSB_CLK */
|
||||
/* E10 : USB2_OCB_1_GP_BSSB_DI */
|
||||
/* E11 : USB2_OCB_2 */
|
||||
/* E12 : USB2_OCB_3 */
|
||||
/* E13 : DDSP_HPD_0_DISP_MISC_0 */
|
||||
/* E14 : DDSP_HPD_0_DISP_MISC_1 */
|
||||
/* E15 : DDSP_HPD_0_DISP_MISC_2 */
|
||||
/* E16 : EMMC_EN */
|
||||
PAD_CFG_GPO(GPP_E16, 1, PLTRST),
|
||||
/* E17 : EDP_HPD_DISP_MISC_4 */
|
||||
/* E18 : DDPB_CTRLCLK */
|
||||
/* E19 : DDPB_CTRLDATA */
|
||||
/* E20 : DDPC_CTRLCLK */
|
||||
/* E21 : DDPC_CTRLDATA */
|
||||
/* E22 : DDPD_CTRLCLK */
|
||||
/* E23 : DDPD_CTRLDATA */
|
||||
|
||||
/* F0 : CNV_GNSS_PA_BLANKING */
|
||||
PAD_CFG_GPI(GPP_F0, NONE, PLTRST),
|
||||
/* F1 : CNV_GNSS_FAT */
|
||||
PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP),
|
||||
/* F2 : CNV_GNSS_SYSCK */
|
||||
PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
|
||||
/* F3 : GPP_F_3 */
|
||||
PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),
|
||||
/* F4 : CNV_BRI_DT_UART0_RTSB */
|
||||
/* F5 : CNV_BRI_RSP_UART0_RXD */
|
||||
/* F6 : CNV_RGI_DT_UART0_TXD */
|
||||
/* F7 : CNV_RGI_DT_RSP_UART9_CTSB */
|
||||
/* F8 : CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1),
|
||||
/* F9 : CNV_MFUART2_TXD */
|
||||
PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1),
|
||||
/* F10 : GPP_F_10 */
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
/* F11 : EMMC_CMD */
|
||||
/* F12 : EMMC_DATA0 */
|
||||
/* F13 : EMMC_DATA1 */
|
||||
/* F14 : EMMC_DATA2 */
|
||||
/* F15 : EMMC_DATA3 */
|
||||
/* F16 : EMMC_DATA4 */
|
||||
/* F17 : EMMC_DATA5 */
|
||||
/* F18 : EMMC_DATA6 */
|
||||
/* F19 : EMMC_DATA9 */
|
||||
/* F20 : EMMC_RCLK */
|
||||
/* F21 : EMMC_CLK */
|
||||
/* F22 : EMMC_RESETB */
|
||||
/* F23 : BIOS_REC */
|
||||
PAD_CFG_GPI(GPP_F23, UP_20K, DEEP),
|
||||
/* G0 : SD3_D2 */
|
||||
/* G1 : SD3_D0_SD4_RCLK_P */
|
||||
/* G2 : SD3_D1_SD4_RCLK_N */
|
||||
/* G3 : SD3_D2 */
|
||||
/* G4 : SD3_D3 */
|
||||
/* G5 : SD3_CDB */
|
||||
PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),
|
||||
/* G6 : SD3_CLK */
|
||||
/* G7 : SD3_WP */
|
||||
PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
|
||||
|
||||
/* H0 : SSP2_SCLK */
|
||||
/* H1 : SSP2_SFRM */
|
||||
/* H2 : SSP2_TXD */
|
||||
/* H3 : SSP2_RXD */
|
||||
/* H4 : I2C2_SDA */
|
||||
/* H5 : I2C2_SCL */
|
||||
/* H6 : I2C3_SDA */
|
||||
PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),
|
||||
/* H7 : I2C3_SCL */
|
||||
PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),
|
||||
/* H8 : I2C4_SDA */
|
||||
/* H9 : I2C4_SCL */
|
||||
/* H10 : I2C5_SDA_ISH_I2C2_SDA */
|
||||
PAD_CFG_GPO(GPP_H10, 1, PLTRST),
|
||||
/* H11 : I2C5_SCL_ISH_I2C2_SCL */
|
||||
PAD_CFG_GPO(GPP_H11, 1, PLTRST),
|
||||
/* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */
|
||||
PAD_CFG_GPO(GPP_H12, 1, PLTRST),
|
||||
/* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */
|
||||
PAD_CFG_GPO(GPP_H13, 1, PLTRST),
|
||||
/* H14 : M2_SKT2_CFG_2 */
|
||||
PAD_CFG_GPO(GPP_H14, 0, PLTRST),
|
||||
/* H15 : M2_SKT2_CFG_3 */
|
||||
PAD_CFG_GPO(GPP_H15, 1, PLTRST),
|
||||
/* H16 : CAM5_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_H16, 1, PLTRST),
|
||||
/* H17 : CAM5_FLASH_STROBE */
|
||||
PAD_CFG_GPO(GPP_H17, 1, PLTRST),
|
||||
/* H18 : BOOTMPC */
|
||||
/* H19 : TIMESYNC_0 */
|
||||
PAD_CFG_GPO(GPP_H19, 1, PLTRST),
|
||||
/* H20 : IMGCLKOUT_1 */
|
||||
/* H21 : GPPC_H_21 */
|
||||
/* H22 : GPPC_H_22 */
|
||||
PAD_CFG_GPO(GPP_H22, 1, PLTRST),
|
||||
/* H23 : GPPC_H_23 */
|
||||
|
||||
/* GPD */
|
||||
/* GPD_0 : BATLOWB */
|
||||
/* GPD_1 : ACPRESENT */
|
||||
/* GPD_2 : LAN_WAKEB */
|
||||
/* GPD_3 : PWRBTNB */
|
||||
/* GPD_4 : SLP_S3B */
|
||||
/* GPD_5 : SLP_S4B */
|
||||
/* GPD_6 : SLP_AB */
|
||||
/* GPD_7 : GPD_7 */
|
||||
/* GPD-8 : SUSCLK */
|
||||
/* GPD-9 : SLP_WLANB */
|
||||
/* GPD-10 : SLP_5B */
|
||||
/* GPD_11 : LANPHYPC */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
};
|
||||
|
||||
const struct pad_config *__weak variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *__weak
|
||||
variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __BASEBOARD_GPIO_H__
|
||||
#define __BASEBOARD_GPIO_H__
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#endif /* __BASEBOARD_GPIO_H__ */
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __BASEBOARD_VARIANTS_H__
|
||||
#define __BASEBOARD_VARIANTS_H__
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table. */
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
/* Seed the NHLT tables with the board specific information. */
|
||||
struct nhlt;
|
||||
void variant_nhlt_init(struct nhlt *nhlt);
|
||||
|
||||
#endif /*__BASEBOARD_VARIANTS_H__ */
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <console/console.h>
|
||||
#include <nhlt.h>
|
||||
#include <soc/nhlt.h>
|
||||
|
||||
void __weak variant_nhlt_init(struct nhlt *nhlt)
|
||||
{
|
||||
/* 1-dmic configuration */
|
||||
if (CONFIG(NHLT_DMIC_1CH_16B) &&
|
||||
!nhlt_soc_add_dmic_array(nhlt, 1))
|
||||
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
|
||||
/* 2-dmic configuration */
|
||||
if (CONFIG(NHLT_DMIC_2CH_16B) &&
|
||||
!nhlt_soc_add_dmic_array(nhlt, 2))
|
||||
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
|
||||
/* 4-dmic configuration */
|
||||
if (CONFIG(NHLT_DMIC_4CH_16B) &&
|
||||
!nhlt_soc_add_dmic_array(nhlt, 4))
|
||||
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
|
||||
|
||||
if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT))
|
||||
{
|
||||
/* Dialog for Headset codec.
|
||||
* Headset codec is bi-directional but uses the same configuration
|
||||
* settings for render and capture endpoints.
|
||||
*/
|
||||
if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))
|
||||
printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
|
||||
|
||||
/* MAXIM Smart Amps for left and right speakers. */
|
||||
if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1))
|
||||
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
|
||||
}
|
||||
|
||||
if (CONFIG(INCLUDE_SND_MAX98373_NHLT) &&
|
||||
!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
|
||||
printk(BIOS_ERR, "Added Maxim_98373 codec.\n");
|
||||
}
|
||||
|
|
@ -1,161 +0,0 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
|
||||
register "PchHdaDspEnable" = "1"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[1]" = "1"
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpEnable[3]" = "1"
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpEnable[11]" = "1"
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpEnable[13]" = "1"
|
||||
register "PcieRpEnable[14]" = "1"
|
||||
register "PcieRpEnable[15]" = "1"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "8"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
|
||||
register "PcieClkSrcUsage[3]" = "13"
|
||||
register "PcieClkSrcUsage[4]" = "4"
|
||||
register "PcieClkSrcUsage[5]" = "14"
|
||||
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
# Enable S0ix
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
|
||||
#| I2C3 | Audio |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_STANDARD,
|
||||
.rise_time_ns = 104,
|
||||
.fall_time_ns = 52,
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.3 on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "PME_B0_EN_BIT"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # CNVi wifi
|
||||
device pci 14.5 on end # SDCard
|
||||
device pci 15.0 on end # I2C #0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 on
|
||||
chip drivers/i2c/max98373
|
||||
register "interleave_mode" = "1"
|
||||
register "vmon_slot_no" = "4"
|
||||
register "imon_slot_no" = "5"
|
||||
register "uid" = "0"
|
||||
register "desc" = ""Right Speaker Amp""
|
||||
register "name" = ""MAXR""
|
||||
device i2c 32 on end
|
||||
end
|
||||
end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
|
||||
register "PcieRpSlotImplemented[0]" = "1"
|
||||
end
|
||||
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
|
||||
register "PcieRpSlotImplemented[4]" = "1"
|
||||
end
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on # PCI Express Port 9
|
||||
register "PcieRpSlotImplemented[8]" = "1"
|
||||
end
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
|
|
@ -1,181 +0,0 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
|
||||
register "PchHdaDspEnable" = "1"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
register "PchHdaAudioLinkSsp0" = "1"
|
||||
register "PchHdaAudioLinkSsp1" = "1"
|
||||
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[1]" = "1"
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpEnable[3]" = "1"
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpEnable[11]" = "1"
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpEnable[13]" = "1"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[1]" = "8"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
|
||||
register "PcieClkSrcUsage[3]" = "14"
|
||||
register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[5]" = "1"
|
||||
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
# Enable S0ix
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.3 on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "PME_B0_EN_BIT"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # CNVi wifi
|
||||
device pci 14.5 on end # SDCard
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ALPS0001""
|
||||
register "generic.desc" = ""Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
|
||||
register "hid_desc_reg_offset" = "0x1"
|
||||
device i2c 2C on end
|
||||
end
|
||||
end # I2C 0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 on
|
||||
chip drivers/i2c/max98373
|
||||
register "vmon_slot_no" = "4"
|
||||
register "imon_slot_no" = "5"
|
||||
register "uid" = "0"
|
||||
register "desc" = ""RIGHT SPEAKER AMP""
|
||||
register "name" = ""MAXR""
|
||||
device i2c 31 on end
|
||||
end
|
||||
chip drivers/i2c/max98373
|
||||
register "vmon_slot_no" = "6"
|
||||
register "imon_slot_no" = "7"
|
||||
register "uid" = "1"
|
||||
register "desc" = ""LEFT SPEAKER AMP""
|
||||
register "name" = ""MAXL""
|
||||
device i2c 32 on end
|
||||
end
|
||||
chip drivers/i2c/da7219
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20)"
|
||||
register "btn_cfg" = "50"
|
||||
register "mic_det_thr" = "500"
|
||||
register "jack_ins_deb" = "20"
|
||||
register "jack_det_rate" = ""32ms_64ms""
|
||||
register "jack_rem_deb" = "1"
|
||||
register "a_d_btn_thr" = "0xa"
|
||||
register "d_b_btn_thr" = "0x16"
|
||||
register "b_c_btn_thr" = "0x21"
|
||||
register "c_mic_btn_thr" = "0x3e"
|
||||
register "btn_avg" = "4"
|
||||
register "adc_1bit_rpt" = "1"
|
||||
register "micbias_lvl" = "2600"
|
||||
register "mic_amp_in_sel" = ""diff""
|
||||
device i2c 1a on end
|
||||
end
|
||||
end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
|
||||
register "PcieRpSlotImplemented[0]" = "1"
|
||||
end
|
||||
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
|
||||
register "PcieRpSlotImplemented[4]" = "1"
|
||||
end
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on # PCI Express Port 9
|
||||
register "PcieRpSlotImplemented[8]" = "1"
|
||||
end
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on
|
||||
chip drivers/generic/max98357a
|
||||
register "hid" = ""MX98357A""
|
||||
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
|
|
@ -1,25 +1,6 @@
|
|||
config SOC_INTEL_CANNONLAKE_BASE
|
||||
bool
|
||||
|
||||
config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
|
||||
bool
|
||||
default y if SOC_INTEL_CANNONLAKE_BASE && !SOC_INTEL_CANNONLAKE
|
||||
help
|
||||
Single Kconfig option to select common base Cannonlake support.
|
||||
This Kconfig will help to select majority of CNL SoC features.
|
||||
Major difference that exist today between
|
||||
SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig
|
||||
are in FSP Header Files. Hence this Kconfig might help to select
|
||||
required SoC support FSP headers. Any future Intel SoC would
|
||||
like to make use of CNL support might just select this Kconfig.
|
||||
|
||||
config SOC_INTEL_CANNONLAKE
|
||||
bool
|
||||
select SOC_INTEL_CANNONLAKE_BASE
|
||||
select MICROCODE_BLOB_NOT_IN_BLOB_REPO
|
||||
help
|
||||
Intel Cannonlake support
|
||||
|
||||
config SOC_INTEL_COFFEELAKE
|
||||
bool
|
||||
select SOC_INTEL_CANNONLAKE_BASE
|
||||
|
|
@ -89,7 +70,6 @@ config CPU_SPECIFIC_OPTIONS
|
|||
select HAVE_FSP_GOP
|
||||
select HAVE_FSP_LOGO_SUPPORT
|
||||
select HAVE_SMI_HANDLER
|
||||
select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
|
||||
select IDT_IN_EVERY_STAGE
|
||||
select INTEL_DESCRIPTOR_MODE_CAPABLE
|
||||
select INTEL_GMA_ACPI
|
||||
|
|
@ -338,7 +318,6 @@ config FSP_HEADER_PATH
|
|||
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2
|
||||
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S
|
||||
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V
|
||||
default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE
|
||||
|
||||
config FSP_FD_PATH
|
||||
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
|
||||
|
|
|
|||
|
|
@ -89,9 +89,6 @@ struct soc_intel_cannonlake_config {
|
|||
enum {
|
||||
SaGv_Disabled,
|
||||
SaGv_FixedLow,
|
||||
#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
|
||||
SaGv_FixedMid,
|
||||
#endif
|
||||
SaGv_FixedHigh,
|
||||
SaGv_Enabled,
|
||||
} SaGv;
|
||||
|
|
|
|||
|
|
@ -177,14 +177,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
|
|||
msr_t msr1;
|
||||
msr_t msr2;
|
||||
|
||||
/*
|
||||
* CFL and WHL CPU die are based on KBL CPU so we need to
|
||||
* have this check, where CNL CPU die is not based on KBL CPU
|
||||
* so skip this check for CNL.
|
||||
*/
|
||||
if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* If PRMRR/SGX is supported the FIT microcode load will set the msr
|
||||
* 0x08b with the Patch revision id one less than the id in the
|
||||
|
|
|
|||
|
|
@ -73,9 +73,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
|
|||
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
|
||||
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
|
||||
|
||||
#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
|
||||
m_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
|
||||
#endif
|
||||
|
||||
if (config->cpu_ratio_override) {
|
||||
m_cfg->CpuRatio = config->cpu_ratio_override;
|
||||
|
|
|
|||
|
|
@ -1,67 +0,0 @@
|
|||
/** @file
|
||||
Header file for Firmware Version Information
|
||||
|
||||
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License which accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
|
||||
#define _FIRMWARE_VERSION_INFO_HOB_H_
|
||||
|
||||
#include <Uefi/UefiMultiPhase.h>
|
||||
#include <Pi/PiBootMode.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// Firmware Version Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 MajorVersion;
|
||||
UINT8 MinorVersion;
|
||||
UINT8 Revision;
|
||||
UINT16 BuildNumber;
|
||||
} FIRMWARE_VERSION;
|
||||
|
||||
///
|
||||
/// Firmware Version Information Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
|
||||
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
|
||||
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
|
||||
} FIRMWARE_VERSION_INFO;
|
||||
|
||||
#ifndef __SMBIOS_STANDARD_H__
|
||||
///
|
||||
/// The Smbios structure header.
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Handle;
|
||||
} SMBIOS_STRUCTURE;
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Firmware Version Information HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
|
||||
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
|
||||
UINT8 Count; ///< Offset 28 Number of FVI elements included.
|
||||
///
|
||||
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
|
||||
///
|
||||
} FIRMWARE_VERSION_INFO_HOB;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _FIRMWARE_VERSION_INFO_HOB_H_
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPUPD_H__
|
||||
#define __FSPUPD_H__
|
||||
|
||||
#include <FspEas.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
#define FSPT_UPD_SIGNATURE 0x545F4450554C4E43 /* 'CNLUPD_T' */
|
||||
|
||||
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E43 /* 'CNLUPD_M' */
|
||||
|
||||
#define FSPS_UPD_SIGNATURE 0x535F4450554C4E43 /* 'CNLUPD_S' */
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,136 +0,0 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPTUPD_H__
|
||||
#define __FSPTUPD_H__
|
||||
|
||||
#include <FspUpd.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
|
||||
/** Fsp T Core UPD
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
UINT32 MicrocodeRegionBase;
|
||||
|
||||
/** Offset 0x0024
|
||||
**/
|
||||
UINT32 MicrocodeRegionSize;
|
||||
|
||||
/** Offset 0x0028
|
||||
**/
|
||||
UINT32 CodeRegionBase;
|
||||
|
||||
/** Offset 0x002C
|
||||
**/
|
||||
UINT32 CodeRegionSize;
|
||||
|
||||
/** Offset 0x0030
|
||||
**/
|
||||
UINT8 Reserved[16];
|
||||
} FSPT_CORE_UPD;
|
||||
|
||||
/** Fsp T Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0040 - PcdSerialIoUartDebugEnable
|
||||
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
|
||||
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
||||
**/
|
||||
UINT8 PcdSerialIoUartDebugEnable;
|
||||
|
||||
/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
|
||||
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
|
||||
Core interface, it cannot be used for debug purpose.
|
||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 PcdSerialIoUartNumber;
|
||||
|
||||
/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT
|
||||
Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is
|
||||
set to UART0.
|
||||
0:default pins, 1:pins muxed with CNV_BRI/RGI
|
||||
**/
|
||||
UINT8 PcdSerialIoUart0PinMuxing;
|
||||
|
||||
/** Offset 0x0043
|
||||
**/
|
||||
UINT8 UnusedUpdSpace0;
|
||||
|
||||
/** Offset 0x0044
|
||||
**/
|
||||
UINT32 PcdSerialIoUartInputClock;
|
||||
|
||||
/** Offset 0x0048 - Pci Express Base Address
|
||||
Base address to be programmed for Pci Express
|
||||
**/
|
||||
UINT64 PcdPciExpressBaseAddress;
|
||||
|
||||
/** Offset 0x0050 - Pci Express Region Length
|
||||
Region Length to be programmed for Pci Express
|
||||
**/
|
||||
UINT32 PcdPciExpressRegionLength;
|
||||
|
||||
/** Offset 0x0054
|
||||
**/
|
||||
UINT8 ReservedFsptUpd1[44];
|
||||
} FSP_T_CONFIG;
|
||||
|
||||
/** Fsp T UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPT_CORE_UPD FsptCoreUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSP_T_CONFIG FsptConfig;
|
||||
|
||||
/** Offset 0x0080
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPT_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -1,270 +0,0 @@
|
|||
/** @file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
@copyright
|
||||
Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
#include <Uefi/UefiMultiPhase.h>
|
||||
#include <Pi/PiBootMode.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
#define MAX_NODE 1
|
||||
#define MAX_CH 2
|
||||
#define MAX_DIMM 2
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
///
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcChannelSts enum in MRC
|
||||
//
|
||||
#ifndef CHANNEL_NOT_PRESENT
|
||||
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||
#endif
|
||||
#ifndef CHANNEL_DISABLED
|
||||
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||
#endif
|
||||
#ifndef CHANNEL_PRESENT
|
||||
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef bmCold
|
||||
#define bmCold 0 // Cold boot
|
||||
#endif
|
||||
#ifndef bmWarm
|
||||
#define bmWarm 1 // Warm boot
|
||||
#endif
|
||||
#ifndef bmS3
|
||||
#define bmS3 2 // S3 resume
|
||||
#endif
|
||||
#ifndef bmFast
|
||||
#define bmFast 3 // Fast boot
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR4
|
||||
#define MRC_DDR_TYPE_DDR4 0
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_DDR3
|
||||
#define MRC_DDR_TYPE_DDR3 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR3
|
||||
#define MRC_DDR_TYPE_LPDDR3 2
|
||||
#endif
|
||||
#ifndef CPU_CFL//CNL
|
||||
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||
#define MRC_DDR_TYPE_LPDDR4 3
|
||||
#endif
|
||||
#else//CFL
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 3
|
||||
#endif
|
||||
#endif//CPU_CFL-endif
|
||||
|
||||
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
} MRC_CH_TIMING;
|
||||
|
||||
typedef struct {
|
||||
UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
|
||||
UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
|
||||
UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
|
||||
UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
|
||||
} MRC_TA_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||
UINT8 Ratio;
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
<b>Revision 2:</b>
|
||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT32 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
#ifdef CPU_CFL
|
||||
UINT32 GdxcIotBase;
|
||||
UINT32 GdxcIotSize;
|
||||
UINT32 GdxcMotBase;
|
||||
UINT32 GdxcMotSize;
|
||||
#endif //CPU_CFL
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
Loading…
Reference in a new issue