nb/intel/nehalem: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions. Change-Id: Ib7e399b5186aa704d0388c4a4b18480f2e3799f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -22,6 +22,7 @@
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#include <device/pci_ops.h>
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#include <cpu/x86/msr.h>
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#include <cbmem.h>
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#include <cf9_reset.h>
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#include <arch/cbfs.h>
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#include <ip_checksum.h>
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#include <pc80/mc146818rtc.h>
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@ -3681,8 +3682,7 @@ void chipset_init(const int s3resume)
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if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) {
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printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
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MCHBAR8(0x2ca8) = 0;
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outb(0x6, 0xcf9);
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halt();
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system_reset();
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}
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#if 0
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if (!s3resume) {
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@ -3907,8 +3907,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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printk(BIOS_INFO,
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"Interrupted RAM init, reset required.\n");
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outb(0x6, 0xcf9);
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halt();
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system_reset();
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}
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}
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@ -4346,8 +4345,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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"Couldn't find training data. Rebooting\n");
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reg32 = inl(DEFAULT_PMBASE + 0x04);
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outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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outb(0xe, 0xcf9);
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halt();
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full_reset();
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}
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int tm;
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info.training = *info.cached_training;
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@ -4788,7 +4786,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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/* Failed S3 resume, reset to come up cleanly */
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outb(0xe, 0xcf9);
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halt();
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full_reset();
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}
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}
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