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soc/xeon_sp/cpx: Define MSR PPIN related registers 

These changes are in accordance with the documentation:
[*] page 208-209
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Tested on OCP DeltaLake with change
https://review.coreboot.org/c/coreboot/+/40308/

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This commit is contained in:
Johnny Lin 2020-05-12 09:12:40 +08:00 committed by Patrick Georgi
parent db654eae79
commit d4698d94af
1 changed files with 9 additions and 0 deletions
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9
src/soc/intel/xeon_sp/cpx/include/soc/msr.h
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@ -96,4 +96,13 @@
#define EPB_ENERGY_POLICY_SHIFT 3 #define EPB_ENERGY_POLICY_SHIFT 3
#define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT)
/* MSR Protected Processor Inventory Number */
#define MSR_PPIN_CTL 0x04e
#define MSR_PPIN_CTL_LOCK 0x1
#define MSR_PPIN_CTL_ENABLE_SHIFT 1
#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT)
#define MSR_PPIN 0x04f
#define MSR_PPIN_CAP_SHIFT 23
#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT)
#endif /* _SOC_MSR_H_ */ #endif /* _SOC_MSR_H_ */