automatically detect southbridge link. this should allow to get rid of most
of the special resource maps spread over the opteron ports and make the code more generic git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -177,11 +177,26 @@
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static void setup_resource_map(const unsigned int *register_values, int max)
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static void setup_resource_map(const unsigned int *register_values, int max)
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{
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{
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int i;
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int i;
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unsigned int amd8111_link_nr;
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print_debug("setting up resource map....\r\n");
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/*
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* determine the HT link number the southbridge is connected to
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* bits 8-9 of the Unit ID register
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*/
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amd8111_link_nr = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64) & 0x00000300) >> 8;
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print_debug(" AMD8111 southbridge is connected to HT link ");
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print_debug_hex32(amd8111_link_nr);
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print_debug("\r\n");
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print_debug("setting up resource map....\r\n");
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print_debug("setting up resource map....\r\n");
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for(i = 0; i < max; i += 3) {
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for(i = 0; i < max; i += 3) {
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device_t dev;
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device_t dev;
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unsigned where;
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unsigned where;
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unsigned long reg;
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unsigned long reg;
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#if 0
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#if 0
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print_debug_hex32(register_values[i]);
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print_debug_hex32(register_values[i]);
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print_debug(" <-");
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print_debug(" <-");
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@ -193,6 +208,19 @@ static void setup_resource_map(const unsigned int *register_values, int max)
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reg = pci_read_config32(dev, where);
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reg = pci_read_config32(dev, where);
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reg &= register_values[i+1];
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reg &= register_values[i+1];
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reg |= register_values[i+2];
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reg |= register_values[i+2];
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/*
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* set correct HT link to the southbridge
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* otherwise we cut of the acces to the flash we are from
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*
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*/
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if (where == 0xBC)
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reg |= amd8111_link_nr << 4;
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if (where == 0xC4)
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reg |= amd8111_link_nr << 4;
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if (where == 0xE0)
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reg |= amd8111_link_nr << 8;
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pci_write_config32(dev, where, reg);
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pci_write_config32(dev, where, reg);
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#if 0
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#if 0
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reg = pci_read_config32(register_values[i]);
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reg = pci_read_config32(register_values[i]);
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