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mb/google/brya: Add EC I/O decode windows 

BUG=b:180013349
TEST=console shows successful EC <-> SoC communications

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Tim Wawrzynczak 2021-02-11 13:43:02 -07:00 committed by Patrick Georgi
parent ad21d6bfca
commit d4749184c2
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/brya/variants/baseboard/devicetree.cb
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@ -3,6 +3,12 @@ chip soc/intel/alderlake
device lapic 0 on end
end
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628