This patch gets the Epia-CN working without ACPI or APIC.
All devices work, no irq storms. Enjoy. Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Bari Ari
Peter Stuge
parent
3153863567
commit
d4759d0f22
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@ -98,12 +98,14 @@ chip northbridge/via/cn700 # Northbridge
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register "ide0_80pin_cable" = "0"
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register "ide1_80pin_cable" = "0"
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device pci f.0 on end # IDE
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register "fn_ctrl_lo" = "0x8a"
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register "fn_ctrl_hi" = "0x9d"
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device pci 10.0 on end # USB 1.1
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device pci 10.1 on end # USB 1.1
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device pci 10.2 on end # USB 1.1
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device pci 10.3 on end # USB 1.1
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register "fn_ctrl_lo" = "0x80"
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register "fn_ctrl_hi" = "0x1d"
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device pci 10.0 on end # OHCI
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device pci 10.1 on end # OHCI
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device pci 10.2 on end # OHCI
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device pci 10.3 on end # OHCI
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device pci 10.4 on end # EHCI
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device pci 10.5 on end # UDCI
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device pci 11.0 on # Southbridge LPC
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chip superio/via/vt1211 # Super I/O
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device pnp 2e.0 off # Floppy
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@ -94,7 +94,7 @@ default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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default CROSS_COMPILE = ""
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default CC = "$(CROSS_COMPILE)gcc -m32"
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default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
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default HOSTCC = "gcc"
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##
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@ -55,34 +55,27 @@ static void enable_mainboard_devices(void)
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{
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device_t dev;
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u8 reg;
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/*
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* If I enable SATA, FILO will not find the IDE disk, so I'll disable
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* SATA here. To not conflict with PCI spec, I'll move IDE device
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* from 00:0f.1 to 00:0f.0.
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*/
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT6420_SATA), 0);
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if (dev != PCI_DEV_INVALID) {
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/* Enable PATA. */
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reg = pci_read_config8(dev, 0xd1);
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reg |= 0x08;
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pci_write_config8(dev, 0xd1, reg);
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reg = pci_read_config8(dev, 0x49);
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reg |= 0x80;
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pci_write_config8(dev, 0x49, reg);
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} else {
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print_debug("No SATA device\r\n");
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}
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/* Disable SATA, and PATA device will be 00:0f.0. */
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
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if (dev == PCI_DEV_INVALID)
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die("Southbridge not found!!!\r\n");
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reg = pci_read_config8(dev, 0x50);
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reg |= 0x08;
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pci_write_config8(dev, 0x50, reg);
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die("Southbridge not found!!!\n");
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/* bit=0 means enable function (per CX700 datasheet)
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* 5 16.1 USB 2
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* 4 16.0 USB 1
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* 3 15.0 SATA and PATA
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* 2 16.2 USB 3
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* 1 16.4 USB EHCI
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*/
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pci_write_config8(dev, 0x50, 0x80);
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/* bit=1 means enable internal function (per CX700 datasheet)
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* 3 Internal RTC
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* 2 Internal PS2 Mouse
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* 1 Internal KBC Configuration
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* 0 Internal Keyboard Controller
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*/
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pci_write_config8(dev, 0x51, 0x1d);
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}
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static const struct mem_controller ctrl = {
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@ -366,7 +366,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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/* dram duty control */
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pci_write_config8(ctrl->d0f3, 0xed, 0x10);
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/* SMM and APIC deocoding, we donot use SMM */
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/* SMM and APIC decoding, we do not use SMM */
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reg = 0x29;
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pci_write_config8(ctrl->d0f3, 0x86, reg);
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/* SMM and APIC decoding mirror */
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@ -45,14 +45,12 @@ static void vga_init(device_t dev)
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u8 reg8;
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print_debug("Copying BOCHS Bios to 0xf000\n");
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/* Copy the BOCHs BIOS from 0xFFFFFFFF - ROM_SIZE - BOCHs size (64k) to 0xf0000
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This is for compatibility with the VGA ROM's BIOS callbacks */
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memcpy(0xf0000, (0xFFFFFFFF - ROM_SIZE - 0x10000), 0x10000);
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/* Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
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* This is for compatibility with the VGA ROM's BIOS callbacks */
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memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000);
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printk_debug("Initializing VGA\n");
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pci_write_config8(dev, 0x3c, 0xb);
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/* Set memory rate to 200MHz */
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outb(0x3d, CRTM_INDEX);
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reg8 = inb(CRTM_DATA);
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@ -71,8 +69,6 @@ static void vga_init(device_t dev)
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pci_write_config8(dev, 0x0d, 0x20);
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pci_write_config32(dev,0x10, 0xf4000008);
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pci_write_config32(dev,0x14, 0xfb000000);
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pci_write_config8(dev, 0x3e, 0x02);
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pci_write_config8(dev, 0x3c, 0x0a);
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printk_debug("INSTALL REAL-MODE IDT\n");
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@ -79,8 +79,6 @@ static void vt8237r_enable(struct device *dev)
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pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
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/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
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/* Extend ROM decode to 1MB FFC00000 - FFFFFFFF */
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pci_write_config8(dev, 0x41, 0x7f);
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}
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struct chip_operations southbridge_via_vt8237r_ops = {
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@ -244,10 +244,20 @@ static void vt8237r_init(struct device *dev)
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enables |= 0x80;
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pci_write_config8(dev, 0x6C, enables);
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/* FIXME: Map 4MB of flash into the address space,
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* this should be in CAR call.
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/*
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* ROM decode
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* bit range
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* 7 000E0000h-000EFFFFh
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* 6 FFF00000h-FFF7FFFFh
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* 5 FFE80000h-FFEFFFFFh
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* 4 FFE00000h-FFE7FFFFh
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* 3 FFD80000h-FFDFFFFFh
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* 2 FFD00000h-FFD7FFFFh
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* 1 FFC80000h-FFCFFFFFh
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* 0 FFC00000h-FFC7FFFFh
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* So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
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*/
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/* pci_write_config8(dev, 0x41, 0x7f); */
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pci_write_config8(dev, 0x41, 0x7f);
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/* Set bit 6 of 0x40 (I/O recovery time).
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* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
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@ -271,8 +281,14 @@ static void vt8237r_init(struct device *dev)
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/* ROM memory cycles go to LPC. */
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pci_write_config8(dev, 0x59, 0x80);
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/* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */
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pci_write_config8(dev, 0x5B, 0xb);
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/*
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* bit meaning
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* 3 Bypass APIC De-Assert Message (1=Enable)
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* 1 possibly "INTE#, INTF#, INTG#, INTH# as PCI"
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* bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
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* 0 Dynamic Clock Gating Main Switch (1=Enable)
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*/
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pci_write_config8(dev, 0x5b, 0x9);
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/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */
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pci_write_config8(dev, 0x48, 0x8c);
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@ -22,6 +22,13 @@
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target via_epia_cn
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mainboard via/epia-cn
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option MAXIMUM_CONSOLE_LOGLEVEL=8
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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# coreboot C code runs at this location in RAM
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option _RAMBASE=0x00004000
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#
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# Generate the final ROM like this:
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# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
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