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mb/google/brya: Add new baseboard hades with variants hades 

Add a new baseboard for hades, an Intel RPL based reference design.
Also, add variants for the reference boards hades. This commit is
a stub which only adds the minimum code needed for a successful build.
Need update gpio and memory DQ pins after final shchematic comes out.

BUG=b:269371363
TEST=abuild -a -x -c max -p none -t google/brya -b hades

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Eric Lai 2023-02-15 13:50:04 +08:00
parent 1fcd7f066d
commit d47a104a2d
12 changed files with 303 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/mainboard/google/brya/Kconfig
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@ -62,6 +62,18 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
select TPM_GOOGLE_CR50
select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG
config BOARD_GOOGLE_BASEBOARD_HADES
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
select BOARD_ROMSIZE_KB_32768
select HAVE_SLP_S0_GATE
select MEMORY_SOLDERDOWN
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
select SOC_INTEL_RAPTORLAKE
select SYSTEM_TYPE_LAPTOP
select TPM_GOOGLE_CR50
config BOARD_GOOGLE_BASEBOARD_NISSA
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
@ -95,6 +107,7 @@ config BASEBOARD_DIR
string
default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA
default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK
default "hades" if BOARD_GOOGLE_BASEBOARD_HADES
default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
default "skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS
@ -157,6 +170,7 @@ config DRIVER_TPM_I2C_BUS
default 0x1 if BOARD_GOOGLE_OMNIGUL
default 0x1 if BOARD_GOOGLE_CONSTITUTION
default 0x1 if BOARD_GOOGLE_AURASH
default 0x1 if BOARD_GOOGLE_HADES
config DRIVER_TPM_I2C_ADDR
hex
@ -183,6 +197,7 @@ config MAINBOARD_FAMILY
string
default "Google_Brya" if BOARD_GOOGLE_BASEBOARD_BRYA
default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK
default "Google_Hades" if BOARD_GOOGLE_BASEBOARD_HADES
default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
default "Google_Skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS
@ -229,6 +244,7 @@ config MAINBOARD_PART_NUMBER
default "Omnigul" if BOARD_GOOGLE_OMNIGUL
default "Constitution" if BOARD_GOOGLE_CONSTITUTION
default "Aurash" if BOARD_GOOGLE_AURASH
default "Hades" if BOARD_GOOGLE_HADES
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@ -273,6 +289,7 @@ config VARIANT_DIR
default "omnigul" if BOARD_GOOGLE_OMNIGUL
default "constitution" if BOARD_GOOGLE_CONSTITUTION
default "aurash" if BOARD_GOOGLE_AURASH
default "hades" if BOARD_GOOGLE_HADES
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA

4
src/mainboard/google/brya/Kconfig.name
View File

@ -341,3 +341,7 @@ config BOARD_GOOGLE_CONSTITUTION
config BOARD_GOOGLE_AURASH
bool "-> Aurash"
select BOARD_GOOGLE_BASEBOARD_BRASK
config BOARD_GOOGLE_HADES
bool "-> Hades"
select BOARD_GOOGLE_BASEBOARD_HADES

6
src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc Normal file
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@ -0,0 +1,6 @@
bootblock-y += gpio.c
romstage-y += memory.c
romstage-y += gpio.c
ramstage-y += gpio.c

4
src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb Normal file
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@ -0,0 +1,4 @@
chip soc/intel/alderlake
device domain 0 on
end
end

48
src/mainboard/google/brya/variants/baseboard/hades/gpio.c Normal file
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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <types.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* TODO */
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* TODO */
};
const struct pad_config *__weak variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
const struct pad_config *__weak variant_gpio_override_table(size_t *num)
{
*num = 0;
return NULL;
}
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};
DECLARE_WEAK_CROS_GPIOS(cros_gpios);
const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
*num = 0;
return NULL;
}

73
src/mainboard/google/brya/variants/baseboard/hades/include/baseboard/ec.h Normal file
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@ -0,0 +1,73 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_EC_H__
#define __BASEBOARD_EC_H__
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/*
* EC can wake from S3/S0ix with:
* 1. Lid open
* 2. AC Connect/Disconnect
* 3. Power button
* 4. Key press
* 5. Mode change
*/
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
(MAINBOARD_EC_S3_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
/*
* ACPI related definitions for ASL code.
*/
/* Enable Keyboard Backlight */
#define EC_ENABLE_KEYBOARD_BACKLIGHT
/* Enable MKBP for buttons and switches */
#define EC_ENABLE_MKBP_DEVICE
/* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
#endif /* __BASEBOARD_EC_H__ */

23
src/mainboard/google/brya/variants/baseboard/hades/include/baseboard/gpio.h Normal file
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@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_GPIO_H__
#define __BASEBOARD_GPIO_H__
#include <soc/gpe.h>
#include <soc/gpio.h>
/* TODO: Set the correct values */
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
#define GPE_EC_WAKE GPE0_DW2_17
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E15
/* EC in RW or RO */
#define GPIO_EC_IN_RW GPP_F18
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_F9
/* GPIO IRQ for tight timestamps / wake support */
#define EC_SYNC_IRQ GPP_F17_IRQ
#endif /* __BASEBOARD_GPIO_H__ */

104
src/mainboard/google/brya/variants/baseboard/hades/memory.c Normal file
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@ -0,0 +1,104 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>
/* TODO: Set the correct values */
static const struct mb_cfg baseboard_memcfg = {
.type = MEM_TYPE_LP4X,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = {40, 30, 30, 30, 30},
},
/* DQ byte map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, },
.dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, },
},
.ddr1 = {
.dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, },
.dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, },
},
.ddr2 = {
.dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, },
.dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, },
},
.ddr3 = {
.dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, },
.dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, },
},
.ddr4 = {
.dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, },
.dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, },
},
.ddr5 = {
.dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, },
.dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, },
},
.ddr6 = {
.dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, },
.dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, },
},
.ddr7 = {
.dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, },
.dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, },
},
},
/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
},
.ect = 1, /* Enable Early Command Training */
};
const struct mb_cfg *__weak variant_memory_params(void)
{
return &baseboard_memcfg;
}
int __weak variant_memory_sku(void)
{
/*
* Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_E11
* GPIO_MEM_CONFIG_1 GPP_E2
* GPIO_MEM_CONFIG_2 GPP_E1
* GPIO_MEM_CONFIG_3 GPP_E12
*/
gpio_t spd_gpios[] = {
GPP_E11,
GPP_E2,
GPP_E1,
GPP_E12,
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
bool __weak variant_is_half_populated(void)
{
/* GPIO_MEM_CH_SEL GPP_E13 */
return gpio_get(GPP_E13);
}
void __weak variant_get_spd_info(struct mem_spd *spd_info)
{
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
spd_info->cbfs_index = variant_memory_sku();
}

8
src/mainboard/google/brya/variants/hades/include/variant/ec.h Normal file
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@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/ec.h>
#endif /* MAINBOARD_GPIO_H */

8
src/mainboard/google/brya/variants/hades/include/variant/gpio.h Normal file
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@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __MAINBOARD_GPIO_H__
#define __MAINBOARD_GPIO_H__
#include <baseboard/gpio.h>
#endif /* __MAINBOARD_GPIO_H__ */

4
src/mainboard/google/brya/variants/hades/memory/Makefile.inc Normal file
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@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-or-later
SPD_SOURCES =
SPD_SOURCES += spd/lp4x/set-0/spd-empty.hex # dummy SPD

4
src/mainboard/google/brya/variants/hades/overridetree.cb Normal file
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@ -0,0 +1,4 @@
chip soc/intel/alderlake
device domain 0 on
end
end