intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PM

Enable SDHCI runtime PM since the display flicker due to
SCC Power Gatingis addressed by 0x82 microcode

BRANCH=glados
BUG=chrome-os-partner:44663
TEST=Check if display flicker is gone when SCC is power-gated

Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba
Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3
Original-Signed-off-by: Medha Garima <medha.garima@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329651
Original-Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Original-Tested-by: Jenny Tc <jenny.tc@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331172
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13990
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/intel/kunimitsu/acpi/mainboard.asl

@@ -308,3 +308,22 @@ Scope (\_SB.PCI0.I2C4)
 		}
 	}
 }
+
+Scope (\_SB.PCI0.SDXC)
+{
+	Name (_CRS, ResourceTemplate () {
+		GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
+			 "\\_SB.PCI0.GPIO", 0, ResourceConsumer)
+		{
+			GPIO_SD_CARD_DETECT
+		}
+	})
+
+	Name (_DSD, Package () {
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package () { "cd-gpio", Package () { ^SDXC, 0, 0, 1 } },
+		}
+	})
+}

src/mainboard/intel/kunimitsu/gpio.h

@@ -58,6 +58,9 @@
  */
 #define AUDIO_DB_ID		GPP_E3
 
+/* SD controller needs additional card detect GPIO to support RTD3 */
+#define GPIO_SD_CARD_DETECT	GPP_A7
+
 #ifndef __ACPI__
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {