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Rangeley: Change A, A, A, A INT routing to A, A, A, B 

Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0.  The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0.  On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.

This issue did not affect ACPI interrupt routing.

This is just a workaround, and the root issue still needs to be fixed.

Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12630
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth 2015-12-02 16:24:00 -07:00
parent cf752fe966
commit d49bbff8ff
2 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/intel/littleplains/irqroute.h
View File

@ -41,12 +41,12 @@
PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \
PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \
PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \
PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \
PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \
PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
/*
@ -66,4 +66,4 @@
PIRQ_PIC(G, 14), \
PIRQ_PIC(H, 15)
#endif /* IRQROUTE_H */
#endif /* IRQROUTE_H */

8
src/mainboard/intel/mohonpeak/irqroute.h
View File

@ -34,6 +34,8 @@
* IR13h SATA3.0 INT(A) - PIRQ A
* IR1Fh LPC INT(ABCD) - PIRQ HGBC
*/
/* Devices set as A, A, A, A evaluate as 0, and don't get set */
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \
@ -41,12 +43,12 @@
PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \
PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \
PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \
PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \
PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \
PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
/*
@ -66,4 +68,4 @@
PIRQ_PIC(G, 14), \
PIRQ_PIC(H, 15)
#endif /* IRQROUTE_H */
#endif /* IRQROUTE_H */