diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index 67d35b396f..3329f638be 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -113,7 +113,6 @@ chip soc/intel/cannonlake
 		device pci 16.4 off	end	# Management Engine Interface 3
 		device pci 16.5 off	end	# Management Engine Interface 4
 		device pci 17.0 on		# SATA
-			register "SataMode" = "SATA_AHCI"
 			register "SataSalpSupport" = "1"
 			# Port 2 (J_SSD2)
 			register "SataPortsEnable[1]" = "1"
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 5826f79ba9..7d9d1e64ca 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "SkipExtGfxScan" = "1"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "SATA_AHCI"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsDevSlp[1]" = "1"
 	# Configure devslp pad reset to PLT_RST
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 69e4e7d059..c975b9906c 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -16,7 +16,6 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "SATA_AHCI"
 	register "SataPortsEnable[2]" = "1"
 	register "SataPortsDevSlp[2]" = "1"
 	register "SkipExtGfxScan" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 021feba777..6a807a36b6 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -16,7 +16,6 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "SATA_AHCI"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsEnable[2]" = "1"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
index 571a33637b..6b326f0c63 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
@@ -172,7 +172,6 @@ chip soc/intel/cannonlake
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on	# SATA
-			register "SataMode" = "SATA_AHCI"
 			register "SataPortsEnable[0]" = "1" # 2.5"
 			register "SataPortsEnable[2]" = "1" # m.2
 			register "satapwroptimize" = "1"
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 1f92fec802..3a0758a7c7 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -113,7 +113,6 @@ chip soc/intel/cannonlake
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on	# SATA
-			register "SataMode" = "SATA_AHCI"
 			register "SataSalpSupport" = "1"
 			# Port 2 (J_SSD2)
 			register "SataPortsEnable[1]" = "1"