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mb/*: Remove SATA mode config for CNL based mainboards 

SATA_AHCI is already the default mode for CNL based mainboards.
Therefore, remove its configuration from all related devicetrees.

Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer 2020-12-07 01:33:42 +01:00 committed by Michael Niewöhner
parent 1e3b2ce061
commit d49fafd531
6 changed files with 0 additions and 6 deletions
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1
src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
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@ -113,7 +113,6 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataMode" = "SATA_AHCI"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
# Port 2 (J_SSD2) # Port 2 (J_SSD2)
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"

1
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -20,7 +20,6 @@ chip soc/intel/cannonlake
# FSP configuration # FSP configuration
register "SkipExtGfxScan" = "1" register "SkipExtGfxScan" = "1"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[1]" = "1"
# Configure devslp pad reset to PLT_RST # Configure devslp pad reset to PLT_RST

1
src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -16,7 +16,6 @@ chip soc/intel/cannonlake
# FSP configuration # FSP configuration
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[2]" = "1" register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1" register "SataPortsDevSlp[2]" = "1"
register "SkipExtGfxScan" = "1" register "SkipExtGfxScan" = "1"

1
src/mainboard/google/sarien/variants/sarien/devicetree.cb
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@ -16,7 +16,6 @@ chip soc/intel/cannonlake
# FSP configuration # FSP configuration
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1" register "SataPortsEnable[2]" = "1"

1
src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
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@ -172,7 +172,6 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2 register "SataPortsEnable[2]" = "1" # m.2
register "satapwroptimize" = "1" register "satapwroptimize" = "1"

1
src/mainboard/system76/lemp9/devicetree.cb
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@ -113,7 +113,6 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataMode" = "SATA_AHCI"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
# Port 2 (J_SSD2) # Port 2 (J_SSD2)
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"