GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/sarien: Enable Camarillo Device 

Whiskeylake processor have an internal device called Camarillo
dedicated for thermal management support, turn it on so processor
thermal driver can be loaded.

BUG=N/A
TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0
can be seen.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7
Reviewed-on: https://review.coreboot.org/c/30858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Lijian Zhao 2019-01-11 11:54:09 -08:00 committed by Patrick Georgi
parent 37d4ffb0a5
commit d4a12ec822
2 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -35,6 +35,7 @@ chip soc/intel/cannonlake
register "satapwroptimize" = "1" register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25" register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51" register "tdp_pl2_override" = "51"
register "Device4Enable" = "1"
# Intel Common SoC Config # Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port

1
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -44,6 +44,7 @@ chip soc/intel/cannonlake
register "SlowSlewRateForFivr" = "2" register "SlowSlewRateForFivr" = "2"
register "tdp_pl1_override" = "25" register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51" register "tdp_pl2_override" = "51"
register "Device4Enable" = "1"
# Intel Common SoC Config # Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port